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A New Test Algorithm for Effective Interconnect Testing Among SoC IPs  

김용준 (연세대학교 전기전자공학과)
강성호 (연세대학교 전기전자공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.40, no.1, 2003 , pp. 61-71 More about this Journal
Abstract
Interconnect test for highly integrated environments like SoC, becomes more important as the complexity of a circuit increases. This importance is from two facts, test time and complete diagnosis. Since the interconnect test between IPs is based on the scan technology such as IEEE1149.1 and IEEE P1500, it takes long test time to apply test vectors serially through a long scan chain. Complete diagnosis is another important issue because a defect on interconnects are shown as a defect on a chip. But generally, interconnect test algorithms that need the short test time can not do complete diagnosis and algorithms that perform complete diagnosis need long test time. A new interconnect test algorithm is developed. The new algorithm can provide a complete diagnosis for all faults with shorter test length compared to the previous algorithms.
Keywords
P1500; IEEE 1149.1; Interconnect test;
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  • Reference
1 Maximal Diagnosis for Wiring Networks /
[ Jung-Chen Lieu;Melvin A. Breuer ] / Proc. International Test Conference
2 Diagnosis for Wiring Interconnect /
[ W-t.Cheng;J.L.Lewandowski;E.Wu ] / Proc. International Test Conference
3 IEEE. S. 1149.1-1990, 'IEEE Standard Test Access Port and Boundary Scan Atchitecture', IEEE, 1989
4 Y. Zorian, S. Dey, M. J. Rodgers, 'Test of Future System-on-Chips', Proc. IEEE/ACM International Conference, pp. 392-398, 2000   DOI
5 E. J. Marinissen, S. K. Goel, M. Lousberg, 'Wrapper Design for Embedded Core Test', Proc. International Test Conference, pp. 911-920, 2001   DOI
6 H. Bleeker, P. V. D. Eijnden, F. D. Jong, 'Boundary-Scan Test : A practical Approach,' Kluwer Academic Publishers, 1993, pp.123-172
7 김현진, 신종철, 강성호, '회로 기판상의 연결 테스트에 대한 분할 그룹 워킹 시퀀스,' Trans. KIEEE Vol.47, No.12, pp. 2251-2257, 1998
8 W. K. Kautz, 'Testing of Faults in Wiring Interconnects,' IEEE Trans. Computers, Vol. C 23, No. 4, April, pp. 358-363, 1974
9 Jung-Chen Lieu and Melvin A. Breuer, 'Maximal Diagnosis for Wiring Networks,' Proc. International Test Conference, pp.96-105, 1991
10 W-t. Cheng, J. L. Lewandowski and E. Wu, 'Diagnosis for Wiring Interconnect,' Proc. International Test Conference, pp 565-571, 1990   DOI
11 K. P. Parker, 'The Boundary- Scan Handbook', Kluwer Academic Publishers, 1992, pp. 1-41, 118-129
12 B. I. Dervisoglu, 'A Unified DFT Architecture for use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers', Proc. Design Automation Conference, pp. 53-58, 2001   DOI
13 C. Su, W. Tseng, 'Configuration Free SoC Interconnect BIST Methodology', Proc. International Test Conference, pp. 1033-1038, 2001   DOI