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Delay Fault Test for Interconnection on Boards and SoCs  

Yi, Hyun-Bean (한양대학교 컴퓨터공학과)
Kim, Doo-Young (한양대학교 컴퓨터공학과)
Han, Ju-Hee (한양대학교 컴퓨터공학과)
Park, Sung-Ju (한양대학교 컴퓨터공학과)
Publication Information
Journal of KIISE:Computer Systems and Theory / v.34, no.2, 2007 , pp. 84-92 More about this Journal
Abstract
This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller and simplifies the test procedure and reduces the area overhead.
Keywords
Interconnect Delay Fault; SoC; IEEE 1149.1; IEEE 1500; Multiple Clocks;
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