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An Efficient Test Compression Scheme based on LFSR Reseeding  

Kim, Hong-Sik (Department of Electrical and Electronic Engineering, Yonsei University)
Kim, Hyun-Jin (Department of Electrical and Electronic Engineering, Yonsei University)
Ahn, Jin-Ho (Department of Electronic Engineering, Hoseo University)
Kang, Sung-Ho (Department of Electrical and Electronic Engineering, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.3, 2009 , pp. 26-31 More about this Journal
Abstract
A new LFSR based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, smax, virtually. The performance of a conventional LFSR reseeding scheme highly depends on smax. In this paper, by using different clock frequencies between an LFSR and scan chains, and grouping the scan cells, we could reduce smax virtually. H the clock frequency which is slower than the clock frequency for the scan chain by n times is used for LFSR, successive n scan cells are filled with the same data; such that the number of specified bits can be reduced with an efficient grouping of scan cells. Since the efficiency of the proposed scheme depends on the grouping mechanism, a new graph-based scan cell grouping heuristic has been proposed. The simulation results on the largest ISCAS 89 benchmark circuit show that the proposed scheme requires less memory storage with significantly smaller area overhead compared to the previous test compression schemes.
Keywords
스캔 테스트;테스트 압축;시스템 온 칩;선형 피드백 레지스터;
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1 N. Zacharia, J. Rajski, J. Tyszer, and J. A. Waicukauski, "Two-Dimensional Test Decompressor for Multiple Scan Designs," Proc. International Test Conferences, pp. 186-194, 1996   DOI
2 H. J.- Wunderlich and G. Kiefer, "Bit-Flipping BIST," Proc. of IEEE International Conference on Computer Aided Design, pp. 337-343, 1996   DOI
3 N. A. Touba and E. J. McCluskey, "Altering a Pseudo-Random Bit Sequence for Scan-Based BIST," Proc. of International Test Conference, pp. 167-175, 1996   DOI
4 F. Brglez. C. Gloster, and G. Kedem, "Hardware-based weighted random pattern generation for boundary scan," Proc. of Design Automation Conference, 1989, pp. 264-274   DOI
5 V. D. Agrawal, C. R. Kime, and K. K. Sluja, "A Tutorial on Buit-In Self-Test, Part 1: Principles," IEEE Design and Test of Computers, vol. 10, no. 1, pp. 73-82, March, 1993   DOI   ScienceOn
6 N. A. Touba and E. J. McCluskey, "Test point insertion based on path tracing," Proc. of VLSI Test Symposium, 1996, pp. 2-8   DOI
7 S. Hellebrand, B. Reeb, S. Tamick, and H. J. Wunderlich, "Pattern Generation for a Deterministic BIST Scheme," Proc. International Conference on Computer-Aided Design (ICCAD) , pp. 88-94, 1995   DOI
8 H.-S. Kim, Y. J Kim and S. Kang, "Test-Decompression Mechanism Using a Variable-Length Multiple-Polynomial LFSR," IEEE Trans. on VLSI Systems, vol. 11, no. 4, pp.687-690, Aug., 2003   DOI   ScienceOn
9 H. -S. Kim, J. -K. Lee, and S. Kang, "A New Multiple Weight Set Calculation Algorithm," Proc. of International Test Conference, pp. 878-894, 2001   DOI
10 B. Koenemann, "LFSR-Coded Test Pattern for Scan Designs," Proc. European Test Conference, pp. 237-242, 1991
11 C. V. Krishna, A. Jas, and N. A. Touba, "Test Vector Encoding Using Partial LFSR Reseeding," Proc. International Test Conference, pp. 885-893, 2001   DOI
12 V. S. Iyenhar and D. Brand, "Synthesis and pseudo-random pattern testable designs," Proc. of International Test Conference, 1989, pp. 501-508   DOI
13 P. H. Bardell, W. Mcanney, and J. Savir, "Built-in Test for VLSI : Pseudo-Random Techniques," John Wiely and Sons, NewYork,1987
14 V. D. Agrawal, C. R Kime, and K. K. Sluja, "A Tutorial on Buit-In Self-Test, Part 2: Applications," IEEE Design and Test of Computers, vol. 10, no. 2, pp. 69-77, June, 1993   DOI   ScienceOn