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R. Sankaralingam, R. R. Oruganti and N. A. Touba, 'Static compaction techniques to control scan vector power dissipation,' Proc. VLSI Test Symposium, pp.35-40, 2000
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2 |
A. Jas., C. V. Krishna, and N. A. Touba, 'Hybrid BIST based on weighted pseudo-random testing: a new test resource parti-tioning scheme,' Proc. VLSI Test Symp., pp. 114-120, 2001
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3 |
P. Gonciari, B. m. Al-Hashimi, and N. Nicolici, 'Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression,' Proc. Design Automation Test Eur., pp. 604-611, 2002
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4 |
L. Whetsel, 'Adapting scan architecture for low power operation,' Proc. Int. Test Conf., pp. 863-872, 2000
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P. Gonciari, I. Guiller, C. landrault, S. Pravossoudovitch, H. J. Wunderlich, 'A modified clock scheme for a low power BlST test pattern generator,' Proc. VLSI Test Symp., pp. 302-311, 2001
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6 |
Jas, A., Dasidar, J. G., and Touba, N. A., 'Using an embedded processor for efficient deterministic testing of system-on-a-chip,' Proc. IEEE Int. Conf. on Computer Design(ICCD), pp. 418-423, 1999
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7 |
C. V. Krishna, A. Jas, and N. A. Touba, 'Test vector encoding using partial LFSR reseeding,' Proc. Int. Test Conf., pp. 885-893, 2001
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8 |
Rosinger, P., Gonciari, T., Al-Hashimi, B. and Nicolici, N., 'Simultaneous reduction in volume of test data and power dissipation for systems-on-a-chip,' lEE Electronics Letters 37(24): pp. 1434-1436, 2001
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ScienceOn
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D. Das and N. A. Touba, 'Reducing test data volume using externaI/LBlST hybrid test pa-ttern,' Proc. Int Test Conf., pp. 115-122, 2000
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Ozgur Sinanolu and Alex Orailoglu, 'A novel scan architecture for power-efficient, rapid Test,' Proc. ICCAD, pp. 299-303, 2002
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11 |
I. Hamzaoglu and J. H. Patel, 'Reducing test application time for full scan embedded cores,' 29th Int. Symp. Fault-Tolerant Comp., pp. 260-267, June, 1999
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Chandra, A., and Chakrabarty, K., 'Frequency-directed run-length codes with application to system-on-a-chip test data compression,' Proc. IEEE VLSI Test Symposium, pp. 42-47, 2001
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13 |
Kedarnath J. Balakrishnan and Touba N, A., 'Matrix-based test vector decompression using an embedded processor,' Proc. IEEE Sympo-sium on Defect and Fault Tolerance, pp. 138-146, 2002
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Yamaguchi, T., Tilgner, M., Ishida, M., and Ha, D. S., 'An efficient method for compressing test data,' Proc., International Test Conference, pp. 191-197, 1997
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EI-Maleh, A., Al-Zahir, S., and Khan, E., 'A geometric primitives based compression scheme for testing system-on-a-chip,' Proc. IEEE VLSI Test Symposium, pp. 54-59, 2001
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16 |
Chandra, A., and Chakrabarty, K., 'Test data compression for system-on-a-chip using Golomb codes,' Proc. IEEE VLSI Test Symposium, pp. 113-120, 2000
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A. Chandra and K. Chakrabarty, 'Combining low-power scan testing and test data compression for system-on-a-chip,' Proc. DAC, pp. 166-169, 2001
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Jas, A., Dastidar, J. G., and Touba, N. A., 'Scan vector compression/decompression using stati-stical coding,' Proc. IEEE VLSI Test Sympo-sium, pp. 114-120, 1999
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