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Low Cost SOC(System-On-a-Chip) Testing Method for Reduction of Test Data and Power Dissipation  

Hur Yongmin (Department of Computer System Engineering, Dong Seoul College)
Lin Chi-ho (Department of Computer Science, Semyung University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.12, 2004 , pp. 83-90 More about this Journal
Abstract
This paper proposes an efficient scan testing method for compression of test input data and reduction of test power for SOC. The proposed method determines whether some parts of a test response can be reused as a part of next input test data on the analysis of deterministic test data and its response. Our experimental results show that benchmark circuits have a high similarity between un-compacted deterministic input test data and its response. The proposed testing method achieves the average of 29.4% reduction of power dissipation based on the number of test clock and 69.7% reduction of test data for ISCAS'89 benchmark circuits.
Keywords
scan testing; compression; test power; test data; SOC;
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