• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.317-326
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• 2016

In this paper, a logic eFuse (electrical Fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) using only logic transistors to reduce the development cost and period of OTP memory IPs is designed. To secure the reliability of other IPs than the OTP memory IP, a higher voltage of 2,4V than VDD (=1.5V) is supplied to only eFuse links of eFuse OTP memory cells directly through an external pad FSOURCE coming from test equipment in testing wafers. Also, an eFuse OTP memory cell of which power is supplied through FSOURCE and hence the program power is increased in a two-dimensional memory array of 128 rows by 8 columns being also able to make the decoding logic implemented in small area. The layout size of the designed 1kb eFuse OTP memory IP with the Dongbu HiTek's 110nm CIS process is $295.595{\mu}m{\times}455.873{\mu}m$ ($=0.134mm^2$).

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.405-413
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• 2013

In this paper, a high-reliability differential paired 24-bit eFuse OTP memory with program-verify-read mode for PMICs is designed. In the proposed program-verify-read mode, the eFuse OTP memory can do a sensing margin test with a variable pull-up load in consideration of programmed eFuse resistance variation and can output a comparison result through a PFb (pass fail bar) pin by comparing a programmed datum with its read one. It is verified by simulation results that the sensing resistance is lower with $4k{\Omega}$ in case of the designed differential paired eFuse OTP memory than $50k{\Omega}$ in case of its dual-port eFuse OTP memory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1371-1378
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• 2009

We propose a low-power eFuse one-time programmable (OTP) memory cell based on a logic process. The eFuse OTP memory cell uses separate transistors optimized at program and read mode, and reduces an operation current at read mode by reducing parasitic capacitances existing at both WL and BL. Asynchronous interface, separate I/O, BL SA circuit of digital sensing method are used for a low-power and small-area eFuse OTP memory IP. It is shown by a computer simulation that operation currents at a logic power supply voltage of VDD and at I/O interface power supply voltage of VIO are 349.5${\mu}$A and 3.3${\mu}$A, respectively. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18${\mu}$m generic process is 300 ${\times}$557${\mu}m^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.10
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• pp.2209-2216
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• 2011

In this paper, we design a 32-bit eFuse OTP memory for PMICs using MagnaChip's $0.18{\mu}m$ process. We solve a problem of an electrical shortage between an eFuse link and the VSS of a p-substrate in programming by placing an n-well under the eFuse link. Also, we propose a WL driver circuit which activates the RWL (read word-line) or WWL (write word-line) of a dual-port eFuse OTP memory cell selectively when a decoded WERP (WL enable for read or program) signal is inputted to the eFuse OTP memory directly. Furthermore, we reduce the layout area of the control circuit by removing a delay chain in the BL precharging circuit. We'can obtain an yield of 100% at a program voltage of 5.5V on 94 manufactured sample dies when measured with memory tester equipment.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.722-725
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• 2012

In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory based on a $0.35{\mu}m$ BCD process using differential paired eFuse cells which can sense BL data without a reference voltage and also have smaller sensing resistances of programmed eFuse links. The channel widths of a program transistor of the differential eFuse OTP cell are splitted into $45{\mu}m$ and $120{\mu}m$. Also, we implement a sensing margin test circuit with variable pull-up loads in consideration of variations of the programmed eFuse resistances. It is confirmed by measurement results that the designed 8-bit eFuse OTP memory IP gives a better yield when the channel width is $120{\mu}m$.

• Convergence Security Journal
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• v.15 no.3_1
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• pp.99-105
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• 2015

A typical SRAM-based PUF is used in random number generation and key exchange process. The generated out puts should be preserved, but the values are changed owing to the external environment. This paper presents a new D-PUF logic employing a dual anti-fuse OTP memory to the SRAM-based PUF. The proposed PUF can enhance the reliability of the logic since it can preserve the output values. First, we construct the OTP memory using an anti-fuse. After power up, a SRAM generates the random values owing to the mismatch of cross coupled inverter pair. The generated random values are programed in the proposed anti-fuse ROM. The values that were programed in the ROM at once will not be changed and returned. Thus, the outputs of the proposed D-PUF are not affected by the environment variable such as the operation voltage and temperature variation, etc. Consequently, the reliability of the proposed PUF will be enhanced owing to the proposed dual anti-fuse ROM. Therefore, the proposed D-PUF can be stably operated, in particular, without the powerful ECC in the external environment that are changed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1734-1740
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• 2012

In this paper, we propose a FSOURCE circuit which requires such a small switching current that an eFuse OTP memory can be programmed in the post-package state of the PMIC chips using a single power supply. The proposed FSOURCE circuit removes its short-circuit current by using a non-overlapped clock and reduces its maximum current by reducing the turned-on slope of its driving transistor. Also, we propose a DOUT buffer circuit initializing the output data of the eFuse OTP memory with arbitrary data during the power-on reset mode. We design a 24-bit differential paired eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $381.575{\mu}m{\times}354.375{\mu}m$($=0.135mm^2$).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.11
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• pp.2541-2547
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• 2010

In this paper, we propose a design technique which replaces logic transistors of 1.2V with medium-voltage transistors of 3.3V having small off-leakage current in repetitive block circuits where speed is not an issue, to implement a low-power eFuse OTP memory IP in the stand-by state. In addition, we use dual-port eFuse cells reducing operational current dissipation by reducing capacitances parasitic to RWL (Read word-line) and BL (Bit-line) in the read mode. Furthermore, we propose an equivalent circuit for simulating program power injected to an eFuse from a program voltage. The layout size of the designed 512-bit eFuse OTP memory IP with a 90nm CMOS image sensor process is $342{\mu}m{\times}236{\mu}m$. It is confirmed by measurement experiments on 42 samples with a program voltage of 5V that we get a good result having 97.6 percent of program yield. Also, the minimal operational supply voltage is measured well to be 0.9V.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.168-175
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• 2017

In this paper, a 5V small-area NMOS-diode eFuse OTP memory cell is proposed. This cell which is used in PMICs consists of a 5V NMOS transistor and an eFuse link as a memory part, based on a BCD process. Also, a regulated voltage of V2V ($=2.0V{\pm}10%$) instead of the conventional VDD is used to the pull-up loads of a VREF circuit and a BL S/A circuit to obtain a wider operational voltage range of the eFuse memory cell. When this proposed cells are used in the simulation, their sensing resistances are found to be $15.9k{\Omega}$ and $32.9k{\Omega}$, in the normal read mode and in the program-verify-read mode, respectively. Furthermore, the read current flowing through a non-blown eFuse is restricted to $97.7{\mu}A$. Thus, the eFuse link of a non-blown eFuse OTP memory cell is kept non-blown. The layout area of the designed 1kb eFuse OTP memory IP based on Dongbu HiTek's BCD process is $168.39{\mu}m{\times}479.45{\mu}m(=0.08mm^2)$.