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http://dx.doi.org/10.17661/jkiiect.2020.13.1.64

Design of PMOS-Diode Type eFuse OTP Memory IP  

Kim, Young-Hee (Department of Electronic Engineering, Changwon National University)
Jin, Hongzhou (Department of Electronic Engineering, Changwon National University)
Ha, Yoon-Gyu (Department of Electronic Engineering, Changwon National University)
Ha, Pan-Bong (Department of Electronic Engineering, Changwon National University)
Publication Information
The Journal of Korea Institute of Information, Electronics, and Communication Technology / v.13, no.1, 2020 , pp. 64-71 More about this Journal
Abstract
eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.
Keywords
Analog Trimming; PMOS-diode; Power Semiconductor; eFuse; OTP;
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