1 |
Comparison of Embedded Non-Volatile Memory Technologies and Their Applications[Internet]. Available: http://www.kilopass.com/wp-content/uploads/2010/04/comparison_of_embedded_nvm.pdf.
|
2 |
EMBEDDED NON -VOLATILE MEMORY[Internet]. Available: http://www.umc.com/english/pdf/eNVM_DM.pdf.
|
3 |
APPLICATION[Internet]. Available: http://www.sidense.com/applications.
|
4 |
T. H. Kim, L. Z. Li, O. Y. Shim, M. H. Park, P. B. Ha, and Y. H. Kim, "Design of Synchronous 256-bit OTP Memory," KIMICS, vol. 12, no. 7, pp. 1227-1234, July 2008.
|
5 |
G. S. Cho, M. Y. Kim, M. C. Kang, J. H. jang, P. B. Ha, and Y. H. Kim, "Design of an 8-Bit eFuse One-Time Programmable Memory IP Using an External Voltage," KIMICS, vol. 14, no. 1, pp. 183-190, Jan. 2009.
|
6 |
J. Safran, A. Leslie, G. Fredeman, C. Kothandaraman, A. Cestero, X. Chen, R. Rajeevakumar, D. K. Kim, Y. Z. Li, D. Moy, N. Robson, T. Kirihata, and S. Iyer, "A Compact eFuse Programmable Array Memory for SOI CMOS," Digest of Technical Papers, Symposium on VLSI Circuits, pp. 72-73, Jun. 2007.
|
7 |
J. H. Kim, J. H. Jang, L. Y. Jin, P. B. Ha, and Y. H. Kim, "Design of low-power OTP memory IP and its measurement," KIMICS, vol. 14, no. 11, pp. 2541-2547, Nov. 2010.
|
8 |
S. H. Kulkarni, Z. Chen, B. Srinivasan, B. Pedersen, U. Bhattacharya, and K. Zhang, "Low-Voltage Metal-Fuse Technology Featuring a 1.6V-Programmable 1T1R Bit Cell with an Integrated 1V Charge Pump in 22nm Tri-Gate Process," Digest of Technical Papers, Symposium on VLSI Circuits, pp. C174-C175, Jun. 2015.
|
9 |
G. Uhlmann, T. Aipperspach, T. Kirihata, Chandrasekharan, Kothandaraman, Y. Z. Li, C. Paone, B. Reed, N. Robson, J. Safran, D. Schmitt, and S. Iyer, "A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS," Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 406-407, Feb. 2008.
|
10 |
T. Kirihata et al, Electronic Fuse Cell and Array, U.S. Patent 0253220, Armonk, N.Y., 2014.
|
11 |
J. H. Kim, D. H. Kim, L. Y. Jin, P. B. Ha, and Y. H. Kim, "Design of 1-Kb eFuse OTP Memory IP with Reliability Considered," Journal of Semiconductor Technology and Science, vol. 11, no. 2, pp. 88-94, June 2011.
DOI
|
12 |
J. H. Jang, L. Y. Jin, H. G, Jeon, K. I. Kim, P. B. Ha, and Y. H. Kim, "Design of an 8-bit Differential Paired eFuse OTP Memory IP Reducing Sensing Resistance," J. Cent. South Univ.,vol. 19, no. 1, pp. 168-173, Jan. 2012.
DOI
|