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http://dx.doi.org/10.6109/jkiice.2010.14.11.2541

Design of low-power OTP memory IP and its measurement  

Kim, Jung-Ho (창원대학교)
Jang, Ji-Hye (창원대학교)
Jin, Liyan (창원대학교)
Ha, Pan-Bong (창원대학교)
Kim, Young-Hee (창원대학교)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.14, no.11, 2010 , pp. 2541-2547 More about this Journal
Abstract
In this paper, we propose a design technique which replaces logic transistors of 1.2V with medium-voltage transistors of 3.3V having small off-leakage current in repetitive block circuits where speed is not an issue, to implement a low-power eFuse OTP memory IP in the stand-by state. In addition, we use dual-port eFuse cells reducing operational current dissipation by reducing capacitances parasitic to RWL (Read word-line) and BL (Bit-line) in the read mode. Furthermore, we propose an equivalent circuit for simulating program power injected to an eFuse from a program voltage. The layout size of the designed 512-bit eFuse OTP memory IP with a 90nm CMOS image sensor process is $342{\mu}m{\times}236{\mu}m$. It is confirmed by measurement experiments on 42 samples with a program voltage of 5V that we get a good result having 97.6 percent of program yield. Also, the minimal operational supply voltage is measured well to be 0.9V.
Keywords
low-power; eFuse; OTP memory; CMOS image sensor; off-leakage current;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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