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http://dx.doi.org/10.6109/jkiice.2013.17.2.405

Design of High-Reliability Differential Paired eFuse OTP Memory for Power ICs  

Park, Young-Bae (창원대학교)
Jin, Li-Yan (창원대학교)
Choi, In-Hwa (창원대학교)
Ha, Pan-Bong (창원대학교)
Kim, Young-Hee (창원대학교)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.17, no.2, 2013 , pp. 405-413 More about this Journal
Abstract
In this paper, a high-reliability differential paired 24-bit eFuse OTP memory with program-verify-read mode for PMICs is designed. In the proposed program-verify-read mode, the eFuse OTP memory can do a sensing margin test with a variable pull-up load in consideration of programmed eFuse resistance variation and can output a comparison result through a PFb (pass fail bar) pin by comparing a programmed datum with its read one. It is verified by simulation results that the sensing resistance is lower with $4k{\Omega}$ in case of the designed differential paired eFuse OTP memory than $50k{\Omega}$ in case of its dual-port eFuse OTP memory.
Keywords
PMIC; Differential paired eFuse; Program-verify-read Mode; High-reliability;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
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