• IEIE Transactions on Smart Processing and Computing
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• v.5 no.1
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• pp.10-16
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• 2016

In this paper, a design for a fully digital voltage sensor using a 32-nm fin-type field-effect transistor (FinFET) is presented. A new characteristic of the double gate p-type FinFET (p-FinFET) is examined and proven appropriate for sensing voltage variations. On the basis of this characteristic, a novel technique for designing low-power voltage-to-time converters is presented. Then, we develop a digital voltage sensor with a voltage range of 0.7 to 1.1V at a 50-mV resolution. The performance of the proposed sensor is evaluated under a range of voltages and process variations using Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, and the sensor is proven capable of operating under ultra-low power consumption, high linearity, and fairly high-frequency conditions (i.e., 100 MHz).

• Journal of information and communication convergence engineering
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• v.7 no.1
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• pp.57-61
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• 2009

This paper has presented the subthreshold current model of FinFET using the potential variation in the doped channel based on the analytical solution of three dimensional Poisson's equation. The model has been verified by the comparison with the data from 3D numerical device simulator. The variation of subthreshold current with front and back gate bias has been studied. The variation of subthreshold swing and threshold voltage with front and back gate bias has been investigated.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.5
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• pp.296-300
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• 2021

The performance of devices has been improved with fine processes from planar to three-dimensional transistors (e.g., FinFET, NWFET, and MBCFET). There are some problems such as a short channel effect or a self-heating effect occur due to the reduction of the gate-channel length by miniaturization. To solve these problems, we compare and analyze the electrical and thermal characteristics of FinFET and GAAFET devices that are currently used and expected to be further developed in the future. In addition, the optimal structure according to the Fin shape was investigated. GAAFET is a suitable device for use in a smaller scale process than the currently used, because it shows superior electrical and thermal resistance characteristics compared to FinFET. Since there are pros and cons in process difficulty and device characteristics depending on the channel formation structure of GAAFET, we expect a mass-production of fine processes over 5 nm through structural optimization is feasible.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.5
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• pp.394-398
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• 2007

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1497-1502
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• 2013

Recently, the junctionless (JL) transistors realized by a single-type doping process have attracted attention instead of the conventional metal-oxide-semiconductor field-effect transistors (MOSFET). The JL transistor can overcome MOSFET's problems such as the thermal budget and short-channel effect. Thus, the JL transistor is considered as great alternative device for a next generation low standby power silicon system. In this paper, the JL FinFET was simulated with a three dimensional (3D) technology computer-aided design (TCAD) simulator and optimized for DC characteristics according to device dimension and doping concentration. The design variables were the fin width ($W_{fin}$), fin height ($H_{fin}$), and doping concentration ($D_{ch}$). After the optimization of DC characteristics, RF characteristics of JL FinFET were also extracted.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.25-31
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• 2016

Parasitic capacitance and resistance of FinFET transistors are the important components that determine the frequency performance of the circuit. Therefore, the researchers in our group developed more accurate parasitic capacitance and resistance for FinFETs than BSIM-CMG. To verify the RF performance, proposed model was applied to design an LNA that has $S_{21}$ more than 10dB and center frequency more than 60GHz using HSPICE. To verify the accuracy of the proposed model, mixed-mode capability of 3D TCAD simulator Sentaurus was used. $S_{21}$ of LNA was chosen as a reference to estimate the error. $S_{21}$ of proposed model showed 87.5% accuracy compared to that of Sentaurus in 10GHz~100GHz frequency range. The $S_{21}$ accuracy of BSIM-CMG model was 56.5%, so by using the proposed model, the accuracy of the circuit simulator improved by 31%. This results validates the accuracy of the proposed model in RF domain and show that the accuracies of the parasitic capacitance and resistance are critical in accurately predicting the LNA performance.

• Journal of information and communication convergence engineering
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• v.8 no.1
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• pp.107-111
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• 2010

This paper has presented the dependence of the threshold voltage on back gate bias and drain voltage for FinFET. The FinFET has three gates such as the front gate, side and back gate. Threshold voltage is defined as the front gate bias when drain current is 1 micro ampere as the onset of the turn-on condition. In this paper threshold voltage is investigated into the analytical potential model derived from three dimensional Poisson's equation with the variation of the back gate bias and drain voltage. The threshold voltage of a transistor is one of the key parameters in the design of CMOS circuits. The threshold voltage, which described the degree of short channel effects, has been extensively investigated. As known from the down scaling rules, the threshold voltage has been presented in the case that drain voltage is the 1.0V above, which is set as the maximum supply voltage, and the drain induced barrier lowing(DIBL), drain bias dependent threshold voltage, is obtained using this model.

• Proceedings of the Optical Society of Korea Conference
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• 2006.02a
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• pp.183-184
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• 2006

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.6
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• pp.576-580
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• 2022

Semiconductor devices have evolved from 2D planar FETs to 3D bulk FinFETs, with aggressive device scaling. Bulk FinFETs make it possible to suppress short-channel effects. In addition, the use of low-k dielectric materials as a vacuum gate spacer have been suggested to improve the AC characteristics of the bulk FinFET. However, although the vacuum gate spacer is effective, correlation between the vacuum gate spacer and the short-channel-effects have not yet been compared or discussed. Using a 3D TCAD simulator, this paper demonstrates how to optimize bulk FinFETs including a vacuum gate spacer and to suppress short-channel effects.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.33-46
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• 2015

In this paper, we predicts the analog and digital circuit performance of FinFETs that are scaled down following the ITRS(International technology roadmap for semiconductors). For accurate prediction of the circuit performance of scaled down devices, accurate parasitic resistance and capacitance analytical models are developed and their accuracies are within 2 % compared to 3D TCAD simulation results. The parasitic capacitance models are developed using conformal mapping, and the parasitic resistance models are enhanced to include the fin extension length($L_{ext}$) with respect to the default parasitic resistance model of BSIM-CMG. A new algorithm is developed to fit the DC characteristics of BSIM-CMG to the reference DC data. The proposed capacitance and resistance models are implemented inside BSIM-CMG to replace the default parasitic model, and SPICE simulations are performed to predict circuit performances such as $f_T$, $f_{MAX}$, ring oscillators and common source amplifier. Using the proposed parasitic capacitance and resistance model, the device and circuit performances are quantitatively predicted down to 5 nm FinFET transistors. As the FinFET technology scales, due to the improvement in both DC characteristics and the parasitic elements, the circuit performance will improve.