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Accuracy Evaluation of the FinFET RC Compact Parasitic Models through LNA Design

LNA 설계를 통한 FinFET의 RC 기생 압축 모델 정확도 검증

  • Jeong, SeungIk (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, SoYoung (College of Information and Communication Engineering, Sungkyunkwan University)
  • 정승익 (성균관대학교 정보통신대학) ;
  • 김소영 (성균관대학교 정보통신대학)
  • Received : 2016.05.16
  • Accepted : 2016.10.18
  • Published : 2016.11.25

Abstract

Parasitic capacitance and resistance of FinFET transistors are the important components that determine the frequency performance of the circuit. Therefore, the researchers in our group developed more accurate parasitic capacitance and resistance for FinFETs than BSIM-CMG. To verify the RF performance, proposed model was applied to design an LNA that has $S_{21}$ more than 10dB and center frequency more than 60GHz using HSPICE. To verify the accuracy of the proposed model, mixed-mode capability of 3D TCAD simulator Sentaurus was used. $S_{21}$ of LNA was chosen as a reference to estimate the error. $S_{21}$ of proposed model showed 87.5% accuracy compared to that of Sentaurus in 10GHz~100GHz frequency range. The $S_{21}$ accuracy of BSIM-CMG model was 56.5%, so by using the proposed model, the accuracy of the circuit simulator improved by 31%. This results validates the accuracy of the proposed model in RF domain and show that the accuracies of the parasitic capacitance and resistance are critical in accurately predicting the LNA performance.

FinFET의 기생 커패시턴스와 기생저항은 회로의 고주파 성능을 결정하는 매우 중요한 요소이다. 선행 연구에서 BSIM-CMG에 구현된 FinFET의 기생 커패시턴스와 저항 모델보다 더 정확한 압축 모델을 개발하였다. 모델의 정확도를 검증하고, FinFET으로 구현 가능한 RF 회로의 성능을 정확하게 예측하기 위해 $S_{21}$ 10dB 이상 중심 주파수 60GHz 이상을 갖는 Low Noise Amplifier (LNA) 에 설계하였다. 22 nm FinFET 소자의 압축모델에 기반한 HSPICE를 사용하여 예측한 회로 성능의 정확도를 검증하기 위해 3D TCAD simulator인 Sentaurus의 mixed-mode 기능을 사용하여 LNA를 시뮬레이션 하였다. TCAD 시뮬레이션 결과를 정확도 측정의 기준으로 삼아 10GHz~100GHz 대역에서 제안한 모델과 Sentaurus의 $S_{21}$을 비교한 결과 87.5%의 정확도를 달성하였다. 이는 기존의 BSIM-CMG의 기생성분으로 예측한 정확도가 56.5%도임에 비해 31% 향상된 정확도를 보여준다. 이를 통해 FinFET의 기생 성분 모델의 정확도를 RF 영역에서 확인하였고, 정확한 기생 저항과 커패시턴스 모델이 LNA 성능을 정확하게 예측하는데 중요한 것임을 확인하였다.

Keywords

References

  1. Frank, M.M., "High-k/metal gate innovations enabling continued CMOS scaling," 2011 Proceedings of ESSCIRC, pp. 50-58, Sept. 2011.
  2. Jyh-Chyurn Guo, "Halo and LDD Engineering for Multiple VTH High Performance Analog CMOS Devices," IEEE Trans. Semiconductor Manufacturing, vol. 20, no. 3, pp. 313-322, Aug. 2007. https://doi.org/10.1109/TSM.2007.901408
  3. Vaidy Subramanian, Bertrand Parvais, Jonathan Borremans, Abdelkarim Mercha, Dimitri Linten, Piet Wambacq, Josine Loo, Morin Dehan, Cedric Gustin, Nadine Collaert, Stefan Kubicek, Robert Lander, Jacob Hooker, Florence Cubaynes, Stephane Donnay, Malgorzata Jurczak, Guido Groeseneken, Willy Sansen, and Stefaan Decoutere, "Planar Bulk MOSFETS Versus FinFETs:An Analog/RF Perspective," IEEE Transactions on Electron Devices Vol. 53, No. 12, pp. 3071-3077 December 2006. https://doi.org/10.1109/TED.2006.885649
  4. Lee K., An T., Joo S., Kwon K.-W., Kim S., "Modeling of parasitic fringing capacitance in multifin trigate FinFETs." IEEE Transactions Electron Devices, Vol. 60, No. 5, pp. 1786-1789, 2013. https://doi.org/10.1109/TED.2013.2252467
  5. Seok Soon Noh, KeeWon Kwon, and SoYoung Kim, "Analysis of Process and Layout Dependent Analog Performance of FinFET Structure using 3D Device Simulator," The Journal of The Institute of Electrical Engineers of Korea, Vol. 50, No. 4, pp. 795-802, April. 2013.
  6. An, TaeYoon, et al. "Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance." Journal of semiconductor technology and science, Vol. 14, No. 5, pp. 525-536, 2014. https://doi.org/10.5573/JSTS.2014.14.5.525
  7. Choe, Kyeungkeun, TaeYoon An, and SoYoung Kim., "Accurate fringe capacitance model considering RSD and metal contact for realistic FinFETs and circuit performance simulation." Simulation of Semiconductor Processes and Devices (SISPAD), pp. 29-32, Sept. 2014.
  8. KyeungKeun Choe, Kee-Won Kwon, and SoYoung Kim, "Circuit Performance Prediction of Scaled FinFET Following ITRS Roadmap based on Accurate Parasitic Compact Model", Journal of The Institute of Electronics and Information Engineers Vol.52, No.10, October. 2015.
  9. JungHun Kim, SoYoung Kim, "The Effect of Contact Boundary on Bulk Resistance in Hexagonal ShapedSource/Drain in FinFETs" ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications, pp. 366-369, Jan. 2015.
  10. TCAD Sentaurus User's Guide, Synopsys.
  11. BSIM-CMG108.0.0 Technical Manual, Aug. 2014.
  12. Pou-Tou Sun, Shry-Sann Liao, Hung-Liang Lin, Chung-Fong Yang, and Yu-Hsuan Hsiao, "Design of 3.1 to 10.6 GHz Ultra-wideband Low Noise Amplifier with Current Reuse Techniques and Low Power Consumption", Progress In Electromagnetics Research Symposium, pp. 901-905, Beijing, Sept. 2011.
  13. Yi-Jing Lin, Shawn S. H. Hsu, Member, IEEE, Jun-De Jin, and C. Y. Chan, "A 3.1-10.6 GHz Ultra-Wideband CMOS Low Noise Amplifier With Current-Reused Technique", IEEE Microwave and Wireless Components Letters, Vol. 17, No. 3, pp. 232-234, March. 2007. https://doi.org/10.1109/LMWC.2006.890503
  14. Andrea Bevilacqua, Ali M. Niknejad, "An Ultrawideband CMOS Low-Noise Amplifier for 3.1-10.6-GHz Wireless Receivers" IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, December. 2004.
  15. Ismail, A. and A. A. Abidi, "A 3-10-GHz low-noise amplifier with wideband LC-ladder matchingnetwork," IEEE Journal of Solid-State Circuits, Vol. 39, Issue 12, 2269-2277, Dec. 2004. https://doi.org/10.1109/JSSC.2004.836344