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http://dx.doi.org/10.4313/JKEM.2021.34.5.296

Thermal Resistance Characteristics and Fin-Layout Structure Optimization by Gate Contact Area of FinFET and GAAFET  

Cho, Jaewoong (Department of Electrical and Computer Engineering, Sungkyunkwan University)
Kim, Taeyong (Department of Electrical and Computer Engineering, Sungkyunkwan University)
Choi, Jiwon (Department of Electrical and Computer Engineering, Sungkyunkwan University)
Cui, Ziyang (Department of Electrical and Computer Engineering, Sungkyunkwan University)
Xin, Dongxu (Department of Electrical and Computer Engineering, Sungkyunkwan University)
Yi, Junsin (College of Information and Communication Engineering, Sungkyunkwan University)
Publication Information
Journal of the Korean Institute of Electrical and Electronic Material Engineers / v.34, no.5, 2021 , pp. 296-300 More about this Journal
Abstract
The performance of devices has been improved with fine processes from planar to three-dimensional transistors (e.g., FinFET, NWFET, and MBCFET). There are some problems such as a short channel effect or a self-heating effect occur due to the reduction of the gate-channel length by miniaturization. To solve these problems, we compare and analyze the electrical and thermal characteristics of FinFET and GAAFET devices that are currently used and expected to be further developed in the future. In addition, the optimal structure according to the Fin shape was investigated. GAAFET is a suitable device for use in a smaller scale process than the currently used, because it shows superior electrical and thermal resistance characteristics compared to FinFET. Since there are pros and cons in process difficulty and device characteristics depending on the channel formation structure of GAAFET, we expect a mass-production of fine processes over 5 nm through structural optimization is feasible.
Keywords
FinFET; GAAFET; Thermal resistance; DIBL; Self-heating effect;
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