• Title/Summary/Keyword: CMOSFET

Search Result 31, Processing Time 0.026 seconds

Dependence of deep submicron CMOSFET characteristics on shallow source/drain junction depth (얕은 소오스/드레인 접합깊이가 deep submicron CMOSFET 소자 특성에 미치는 영향)

  • 노광명;고요환;박찬광;황성민;정하풍;정명준
    • Journal of the Korean Institute of Telematics and Electronics A
    • /
    • v.33A no.4
    • /
    • pp.112-120
    • /
    • 1996
  • With the MOsES (mask oxide sidewall etch scheme)process which uses the conventional i-line stepper and isotropic wet etching, CMOSFET's with fine gate pattern of 0.1.mu.m CMOSFET device, the screening oxide is deposited before the low energy ion implantation for source/drain extensions and two step sidewall scheme is adopted. Through the characterization of 0.1.mu.m CMOSFET device, it is found that the screening oxide deposition sheme has larger capability of suppressing the short channel effects than two step sidewall schem. In cse of 200.angs.-thick screening oxide deposition, both NMOSFET and PMOSFET maintain good subthreshold characteristics down to 0.1.mu.m effective channel lengths, and show affordable drain saturation current reduction and low impact ionization rates.

  • PDF

PMOSFET Hot Carrier Lifetime Dominated by Hot Hole Injection and Enhanced PMOSFET Degradation than NMOSFET in Nano-Scale CMOSFET Technology (PMOSFET에서 Hot Carrier Lifetime은 Hole injection에 의해 지배적이며, Nano-Scale CMOSFET에서의 NMOSFET에 비해 강화된 PMOSFET 열화 관찰)

  • 나준희;최서윤;김용구;이희덕
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.41 no.7
    • /
    • pp.21-29
    • /
    • 2004
  • Hot carrier degradation characteristics of Nano-scale CMOSFETs with dual gate oxide have been analyzed in depth. It is shown that, PMOSFET lifetime dominate the device lifetime than NMOSFET In Nano-scale CMOSFETs, that is, PMOSFET lifetime under CHC (Channel Hot Carrier) stress is much lower than NMOSFET lifetime under DAHC (Dram Avalanche Hot Carrier) stress. (In case of thin MOSFET, CHC stress showed severe degradation than DAHC for PMOSFET and DAHC than CHC for NMOSFET as well known.) Therefore, the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor in upcoming Nano-scale CMOSFET technology. In case of PMOSFETs, CHC shows enhanced degradation than DAHC regardless of thin and thick PMOSFETs. However, what is important is that hot hole injection rather than hot electron injection play a important role in PMOSFET degradation i.e. threshold voltage increases and saturation drain current decreases due to the hot carrier stresses for both thin and thick PMOSFET. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method. Therefore, suppression of PMOSFET hot carrier degradation or hot hole injection is highly necessary to enhance overall device lifetime or circuit lifetime in Nano-scale CMOSFET technology

Thermal Stability Improvement of Ni-silicide Using Ni-Co alloy for Nano-Scale CMOSFET Technology (나노급 CMOSFET을 윈한 Ni-Co 합금을 이용한 Ni-silicide의 열안정성 개선)

  • Park, Kee-Young;Zhang, Ying-Ying;Jung, Soon-Yen;Li, Shi-Guang;Zhun, Zhong;Lee, Ga-Won;Wang, Jin-Suk;Lee, Hi-Deok
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2007.06a
    • /
    • pp.27-28
    • /
    • 2007
  • In this paper, Ni-Co alloy was used for improvement of thermal stability of Ni silicide. The proposed Ni/Ni-Co structure exhibited wide temperature window of rapid thermal process. Sheet resistance as well as cross-sectional profile showed stable characteristics in spite of high temperature annealing up to $700^{\circ}C$ for 30min. Therefore, the proposed Ni/Ni-Co structure is highly promising for highly thermal immune Ni silicide for nano-scale CMOSFET technology.

  • PDF

Dependence of Low-frequency Noise and Device Characteristics on Initial Oxidation Method of Plasma-nitride Oxide for Nano-scale CMOSFET (Nano-CMOSFET를 위한 플라즈마-질화막의 초기 산화막 성장방법에 따른 소자 특성과 저주파 잡음 특성 분석)

  • Joo, Han-Soo;Han, In-Shik;Goo, Tae-Gyu;Yoo, Ook-Sang;Choi, Won-Ho;Choi, Myoung-Gyu;Lee, Ga-Won;Lee, Hi-Deok
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.20 no.1
    • /
    • pp.1-7
    • /
    • 2007
  • In this paper, two kinds of initial oxidation methods i.e., SLTO(Slow Low Temperature Oxidation: $700^{\circ}C$) and RTO(Rapid Thermal Oxidation: $850^{\circ}C$) are applied prior to the plasma nitridation for ultra thin oxide of RPNO (Remote Plasma Nitrided Oxide). It is observed that SLTO has superior characteristics to RTO such as lower SS(Sub-threshold Slope) and improved Ion-Ioff characteristics. Low frequency noise characteristics of SLTO also showed better than RTO both in linear and saturation regime. It is shown that flicker noise is dominated by carrier number fluctuation in the channel region. Therefore, SLTO is promising for nano-scale CMOS technology with ultra thin gate oxide.

Thermal Stability Improvement of Ni-Silicide on the SOI Substrate Doped B11 for Nano-scale CMOSFET (나노급 CMOSFET을 위한 SOI기판에 도핑된 B1l을 이용한 니켈-실리사이드의 열안정성 개선)

  • Jung, Soon-Yen;Oh, Soon-Young;Lee, Won-Jae;Zhang, Ying-Ying;Zhong, Zhun;Li, Shi-Guang;Kim, Yeong-Cheol;Lee, Ga-Won;Wang, Jin-Suk;Lee, Hi-Deok
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.19 no.11
    • /
    • pp.1000-1004
    • /
    • 2006
  • In this paper, thermal stability of Ni-silicide formed on the SOI substrate with $B_{11}$ has been characterized. The sheet resistance of Ni-silicide on un-doped SOI and $B_{11}$ implanted bulk substrate was increased after the post-silicidation annealing at $700^{\circ}C$ for 30 min. However, in case of $B_{11}$ implanted SOI substrate, the sheet resistance showed stable characteristics after the post-silicidation annealing up to $700^{\circ}C$ for 30 min. The main reason of the excellent property of $B_{11}$ sample is believed to be the retardation of Ni diffusion by the boron and bottom oxide layer of SOI. Therefore, retardation of Ni diffusion is highly desirable lot high performance Ni silicide technology.

Submicron CMOSFET에서 기판 방향에 대한 소자 성능 의존성 분석

  • Park, Ye-Ji;Han, In-Sik;Park, Sang-Uk;Gwon, Hyeok-Min;Bok, Jeong-Deuk;Park, Byeong-Seok;Lee, Hui-Deok
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2009.11a
    • /
    • pp.7-7
    • /
    • 2009
  • In this paper, we investigated the dependence of HCI (Hot Carrier Immunity) degradation and device performance on channel orientation in sub-micron PMOSFET. Although device performance ($I_{D.sat}$ vs. $I_{Off}$) was improved as the transistor angle increased HC immunity was degraded. Therefore, consideration of reliability characteristics as well as dc device performance is highly necessary in channel stress engineering of next generation CMOSFETs.

  • PDF

Thermal Stability Improvement of Ni-Silicide using Ni-Co alloy for Nano-scale CMOSFET (나노급 CMOSFET을 위한 니켈-코발트 합금을 이용한 니켈-실리사이드의 열안정성 개선)

  • Park, Kee-Young;Jung, Soon-Yen;Han, In-Shik;Zhang, Ying-Ying;Zhong, Zhun;Li, Shi-Guang;Lee, Ga-Won;Wang, Jin-Suk;Lee, Hi-Deok
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.21 no.1
    • /
    • pp.18-22
    • /
    • 2008
  • In this paper, the Ni-Co alloy was used for thermal stability estimation comparison with Ni structure. The proposed Ni/Ni-Co structure exhibited wider range of rapid thermal process windows, lower sheet resistance in spite of high temperature annealing up to $700^{\circ}C$ for 30 min, more uniform interface via FE-SEM analysis, NiSi phase peak. Therefore, The proposed Ni/Ni-Co structure is highly promising for highly thermal immune Ni-silicide for nano-scale MOSFET technology.

Analysis of Cuoff Frequency and Maximum Oscillation Frequency Characteristics for $0.13{\mu}m$ CMOSFET ($0.13{\mu}m$ CMOSFET의 차단주파수 및 최대진동주파수 특성 분석)

  • Kim, Jong-HyucK;Lee, Seong-Hearn;Kim, Young-Wug
    • Proceedings of the IEEK Conference
    • /
    • 2006.06a
    • /
    • pp.539-540
    • /
    • 2006
  • The dependence of cutoff frequency and maximum oscillation frequency of $0.13{\mu}m$ CMOS transistors on layout parameters such as the unit gate width and gate finger number is measured and analyzed in this paper. This information will be very useful for high performance RF IC design.

  • PDF

Characterization of the Dependence of the Device on the Channel Stress for Nano-scale CMOSFETs (Nano CMOSFET에서 Channel Stress가 소자에 미치는 영향 분석)

  • Han In-Shik;Ji Hee-Hwan;Kim Kyung-Min;Joo Han-Soo;Park Sung-Hyung;Kim Young-Goo;Wang Jin-Suk;Lee Hi-Deok
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.43 no.3 s.345
    • /
    • pp.1-8
    • /
    • 2006
  • In this paper, reliability (HCI, NBTI) and device performance of nano-scale CMOSFETs with different channel stress were investigated. It was shown that NMOS and PMOS performances were improved by tensile and compressive stress, respectively, as well known. It is shown that improved device performance is attributed to the increased mobility of electrons or holes in the channel region. However, reliability characteristics showed different dependence on the channel stress. Both of NMOS and PMOS showed improved hot carrier lifetime for compressive channel stress. NBTI of PMOS also showed improvement for compressive stress. It is shown that $N_{it}$ generation at the interface of $Si/SiO_2$ has a great effect on the reliability. It is also shown that generation of positive fixed charge has an effect in the NBTI. Therefore, reliability as well as device performance should be considered in developing strained-silicon MOSFET.