• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1089-1095
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• 2005

This paper presents a new low-cost Built-In Self-Test (BIST) circuit for 50Hz low noise amplifier (LNA). The BIST circuit is designed for system-on-chip (SoC) transceiver environment. The proposed BIST circuit measures the LNA specifications such as input impedance, voltage gaih, noise figure, and input return loss all in a single SoC environment.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1004-1007
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• 2005

This paper presents a programmable RF BIST (Built-in Self-Test) circuit for low noise amplifiers. We have developed a new on-chip RF BIST circuit that measures RF parameters of low noise amplifier (LNA) using only DC measurements. The BIST circuit contains test amplifier with programmable capacitor banks and RF peak detectors. The test circuit utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the mathematical equations. Our on-chip BIST can be self programmed for 1.8GHz, 2.4GHz and 5.25GHz LNA for GSM, Bluetooth and IEEE802.11g standards.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.34-41
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• 2007

We popose a programmed on-line to FSM-based Programmable BIST(Buit-In Self-Test) with selected command, to select a test algorithm from a predetermined set of algorithms that are built in the Flash memory BIST. Thus, the proposed scheme greatly simplifies the testing process. Besides, the proposed FSM-based Programmable BIST is more efficient in terms of circuit size and test data to be applied, and it requires less time to configure the Flash memory BIST. We also will develop a programmable Flash memory BIST generator that automatically produces Verilog code of the proposed BIST architecture for a given set of test algorithms. If experiment the proposed method, the proposed method will achieves a good flexibility with smaller circuit size compared with previous methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.610-618
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• 2003

Recently, many deterministic built-in self-test schemes to reduce test time have been researched. These schemes can achieve a good quality test by shortening the whole test process, but require complex algorithms or much hardware. In this paper, a new deterministic BIST scheme is provided that reduces the additional hardware requirements, as well as keeping test time to a minimum. The proposed BIST (Built-In Self-Test) methodology brings about the reduction of the hardware requirements for pseudo-random tests as well. Theoretical study demonstrates the possibility of reducing the hardware requirements for both pseudo-random and deterministic tests, with some explanations and examples. Experimental results show that in the proposed test scheme the hardware requirements for the pseudo-random test and deterministic test are less than in previous research.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.807-810
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• 1998

This paper presents BIST (Built-in self-test) techniques for detection of path delay faults in digital circuits. In the proosed BIST schemes, the shift registers make possible to concurrently generate and compact the latched test data. Therefore the test time is reduced efficiently. By reordering the elements of th shifte register based on the information of the hamming distance of each memory elements in CUt, it is possible to increase the number of path delay faults detected robustly/non-robustly. Experimental results for ISCAS'89 benchmark circuits show the efficiency of the proposed BIST techniques.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.5
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• pp.129-140
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• 2014

BIST(Built-in self test) is to detect various faults of the existing memory and BIRA(Built-in redundancy analysis) is to repair detected faults by allotting spare. Also, BISR(Built-in self repair) which integrates BIST with BIRA, can enhance the whole memory's yield. However, the previous methods were suggested for RAM and are difficult to diagnose disturbance that is NAND-type flash memory's intrinsic fault when used for the NAND-type flash memory with different characteristics from RAM's memory structure. Therefore, this paper suggests a BISD(Built-in self diagnosis) to detect disturbance occurring in the NAND-type flash memory and to diagnose the location of fault, and BISR to repair faulty blocks.

• ETRI Journal
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• v.37 no.4
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• pp.787-792
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• 2015

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.635-641
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• 2004

This paper presents a new low-cost RF Built-In Self-Test (BIST) circuit for measuring transducer voltage gain, noise figure and input impedance of 5.25GHa low noise amplifier (LNA). The BIST circuit is designed using 0.18${\mu}{\textrm}{m}$ SiGe technology. The test technique utilizes input impedance matching and output transient voltage measurements. The technique is simple and inexpensive. Total chip size has additional area of about 18% for BIST circuit.

• ETRI Journal
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• v.28 no.3
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• pp.355-363
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• 2006

This paper presents a low-cost RF parameter estimation technique using a new RF built-in self-test (BIST) circuit and efficient DC measurement for 4.5 to 5.5 GHz low noise amplifiers (LNAs). The BIST circuit measures gain, noise figure, input impedance, and input return loss for an LNA. The BIST circuit is designed using $0.18\;{\mu}m$ SiGe technology. The test technique utilizes input impedance matching and output DC voltage measurements. The technique is simple and inexpensive.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.8
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• pp.1705-1712
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• 2004

This paper presents a new low-cost RF Built-In Self-Test (BIST) circuit for measuring transducer voltage gain, noise figure and input impedance of 5.25GHz low noise amplifier (LNA). The BIST circuit is designed using 0.18${\mu}{\textrm}{m}$ SiGe technology. The test technique utilizes input impedance matching and output transient voltage measurements. The technique is simple and inexpensive. Total chip size has additional area of about 18% for BIST circuit.