Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Newly Developed Mixed-Mode BIST

효율적인 혼합 BIST 방법

  • 김현돈 (연세대학교 전기전자공학과) ;
  • 신용승 (연세대학교 전기전자공학과) ;
  • 김용준 (연세대학교 전기전자공학과) ;
  • 강성호 (연세대학교 전기전자공학과)
  • Published : 2003.08.01
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Abstract

Recently, many deterministic built-in self-test schemes to reduce test time have been researched. These schemes can achieve a good quality test by shortening the whole test process, but require complex algorithms or much hardware. In this paper, a new deterministic BIST scheme is provided that reduces the additional hardware requirements, as well as keeping test time to a minimum. The proposed BIST (Built-In Self-Test) methodology brings about the reduction of the hardware requirements for pseudo-random tests as well. Theoretical study demonstrates the possibility of reducing the hardware requirements for both pseudo-random and deterministic tests, with some explanations and examples. Experimental results show that in the proposed test scheme the hardware requirements for the pseudo-random test and deterministic test are less than in previous research.

테스터를 사용하는 테스트 방법이 매우 비싸고 동작속도에서의 테스트가 어려운 상황에서 BIST의 출현 은 이러한 난점을 해결하는 좋은 방법이다. 하지만, 이러한 BIST에도 해결해야 할 문제점들이 많다. 의사 무작위 테스트시 패턴 카운터와 비트 카운터의 역할이 단순히 카운팅만 하는데 한정되어 있으므로 이들 카운터를 패턴을 생성하는 역할에도 이용함으로써 BIST의 효율을 증대시키고자 한다. 새로운 BIST 구조는 LFSR이 아닌 카운터로 패턴을 생성하고 LFSR로 이의 동작을 무작위하게 또는 의도적으로 조정함으로써 다른 테스트 성능의 저하 없이 테스트 하드웨어를 축소하는 방법을 제안한다. 결정 테스트를 위한 하드웨어가 너무 크게 되는 단점을 해결하고자 본 논문에서의 실험은 실험결과에서 의사 무작위 테스트와 결정 테스트의 성능을 고장검출을, 테스트 시간과 하드웨어 관련 인자들로 표현한다.

Keywords

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