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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Fully Programmable Memory BIST for Commodity DRAMs

  • Kim, Ilwoong (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Jeong, Woosik (Product Development Group, Hynix Semiconductor Inc.) ;
  • Kang, Dongho (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kang, Sungho (Department of Electrical and Electronic Engineering, Yonsei University)
  • Received : 2015.01.16
  • Accepted : 2015.04.21
  • Published : 2015.08.01
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Abstract

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

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References

  1. B. Ismet, O. Caty, and Y. Wong, "Highly Configurable Programmable Built-In Self Test Architecture for High-Speed Memories," IEEE VLSI Test Symp., Palm Springs, CA, USA, May 1-5, 2005, pp. 21-26.
  2. S. Boutobza et al., "Programmable Memory BIST," IEEE Int. Test Conf., Austin, TX, USA, Nov. 8-10, 2005, pp. 1155-1164.
  3. Y. Park et al., "A Flexible Programmable Memory BIST for Embedded Single-Port Memory and Dual-Port Memory," ETRI J., vol. 35, no. 5, Oct. 2013, pp. 808-818. https://doi.org/10.4218/etrij.13.0112.0717
  4. M. Kume et al., "Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI," IEEE Int. Test Conf., Charlotte, NC, USA, Oct. 26-28, 2004, pp. 988-996.
  5. T. Han et al., "High Repair Efficiency BIRA Algorithm with a Line Fault Scheme," ETRI J., vol. 32, no. 4, Aug. 2010, pp. 642-644. https://doi.org/10.4218/etrij.10.0210.0097
  6. Z. Al-Ars and A.J. van de Goor, "Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs," IEEE Trans. Comput., vol. 52, no. 3, Mar. 2003, pp. 293-309. https://doi.org/10.1109/TC.2003.1183945

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