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A Newly Developed Mixed-Mode BIST  

김현돈 (연세대학교 전기전자공학과)
신용승 (연세대학교 전기전자공학과)
김용준 (연세대학교 전기전자공학과)
강성호 (연세대학교 전기전자공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.40, no.8, 2003 , pp. 610-618 More about this Journal
Abstract
Recently, many deterministic built-in self-test schemes to reduce test time have been researched. These schemes can achieve a good quality test by shortening the whole test process, but require complex algorithms or much hardware. In this paper, a new deterministic BIST scheme is provided that reduces the additional hardware requirements, as well as keeping test time to a minimum. The proposed BIST (Built-In Self-Test) methodology brings about the reduction of the hardware requirements for pseudo-random tests as well. Theoretical study demonstrates the possibility of reducing the hardware requirements for both pseudo-random and deterministic tests, with some explanations and examples. Experimental results show that in the proposed test scheme the hardware requirements for the pseudo-random test and deterministic test are less than in previous research.
Keywords
Built in Self Test; deterministic test pattern; LFSR; reseeding;
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