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A Newly Developed Mixed-Mode BIST  

김현돈 (연세대학교 전기전자공학과)
신용승 (연세대학교 전기전자공학과)
김용준 (연세대학교 전기전자공학과)
강성호 (연세대학교 전기전자공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.40, no.8, 2003 , pp. 610-618 More about this Journal
Abstract
Recently, many deterministic built-in self-test schemes to reduce test time have been researched. These schemes can achieve a good quality test by shortening the whole test process, but require complex algorithms or much hardware. In this paper, a new deterministic BIST scheme is provided that reduces the additional hardware requirements, as well as keeping test time to a minimum. The proposed BIST (Built-In Self-Test) methodology brings about the reduction of the hardware requirements for pseudo-random tests as well. Theoretical study demonstrates the possibility of reducing the hardware requirements for both pseudo-random and deterministic tests, with some explanations and examples. Experimental results show that in the proposed test scheme the hardware requirements for the pseudo-random test and deterministic test are less than in previous research.
Keywords
Built in Self Test; deterministic test pattern; LFSR; reseeding;
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  • Reference
1 G. Kiefer and H. J. Wunderlich, 'Using BIST Control for Pattern Generation', in Proc. Int. Test Conf., 1997, pp. 347-355   DOI
2 S. Hellebrand, H. G. Liang and H. J. Wunderlich, 'A Mixed Mode BIST Scheme Based On Reseeding of Folding Counters', in Proc. Int. Test Conf., 2000, pp. 778-784   DOI
3 N. A. Touba and E. J. McCluskey, 'Bit-fixing in pseudorandom sequences for scan BIST', IEEE Trans. Computer-Aided Design, vol. 20, 2001, pp, 545-555   DOI   ScienceOn
4 K. Chakrabarty, B. T. Murray and V. Iyengar, 'Deterministic Built-In Self Test Pattern Generation for High-Performance Circuits using Twisted-Ring Counters', IEEE Trans. VLSI Systems, vol. 8, no. 5, 2000, pp. 633-636   DOI   ScienceOn
5 C. Fagot, P. Girard and C. Landrault, 'On Using Machine Learning for Logic BIST', III Proc. Int. Test Conf., 1997, pp. 338-346   DOI
6 G. Kiefer, H. Wunderlich: 'Deterministic BIST with Multiple Scan Chains', in Proc. Int. Conf., 1998, pp. 1057-1064   DOI
7 S. Wang, 'Low hardware overhead scan based 3-weight weighted random BIST', Proc. Int. Test Conf., 2001, pp. 868-877   DOI
8 N. A. Touba, E. J. McCluskey, 'Altering a pseudo-random bit sequence for scan-based BIST', in Proc. Int. Test Conf., 1996, pp. 167-175   DOI
9 S. B. Akers and W. Jansz, 'Test Set Embedding in Built-In Self-Test Environment', in Proc. Int. Test Conf., 1989, pp. 257-263   DOI
10 C. Fagot, O. Gascuel, P. Girard, C. Landrault, 'On Calculating Efficient LFSR Seeds for Built-In Self Test', Test Workshop. European, 1999, pp. 7-14   DOI
11 S. Hellebrand, H. -J. Wunderlich, O. F. Haberl, 'Generating Pseudo-Exhaustive Vectors for External Testing', in Proc. Int. Test Conf., 1990, pp. 670-679   DOI
12 B. Pouya and N. A. Touba, 'Synthesis of zeroaliasing elementary-tree space compactors', in Proc. IEEE VLSI Test Symp., 1998, pp. 70-77   DOI
13 H. S. Kim, J. K. Lee, S. H. Rang, 'A new multiple weight set calculation algorithm', in Proc. Int. Test Conf., 2001, pp. 878-884   DOI
14 S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois, 'Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers', IEEE Trans. Comput., 1995, pp. 223-233   DOI   ScienceOn
15 H. Lee, S. Rang, 'A new weight set generation algorithm for weighted random pattern generation,' in Proc. Int. Test Conf., 1999, pp. 160-165   DOI
16 C. V. Krishna, A. Jas, N. A. Touba, 'Test vector encoding using partial LFSR reseeding', in Proc. Int. Test Conf., 2001, pp. 885-893   DOI
17 E. Kalligeros, X. Kavousianos, D. Bakalis, D. Nikolos, 'New reseeding technique for LFSR-based test pattern generation', On-line Testing Workshop, 2001, pp. 80-86   DOI
18 S. Hellebrand, S. Tarnick, J. Raj ski, B. Courtois, 'Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift registers', in Proc. Int. Test Conf., 1992, pp. 120-129
19 M. Abramovici, M. A. Breuer and A. D. Fiedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990