• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1111-1116
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• 2011

In this paper, a 60 GHz bidirectional active phase shifter with 130 nm CMOS is presented by replacing CMOS passive switchs in switched-line type phase shifter with Common Gate Amplifier(bidirectional amplifier). Bidirectional active phase shifter is composed of bidirectional amplifier blocks and passive delay line network blocks. The suitable topology of bidirectional amplifier block is CGA(Common Gate Amplifier) topology and matching circuits of input and output are symmetrical due to design same characteristic of it's forward and reverse way. The direction(forward and reverse way) and amplitude of amplification can be controlled by only one bias voltage($V_{DS}$) using combination bias circuit. And passive delay line network blocks are composed of microstrip line. An 1-bit phase shifter is fabricated by Dongbu HiTek 1P8M 130-nm CMOS technology and simulation results present -3 dB average insertion loss and respectively 90 degree and 180 degree phase shift at 60 GHz.

• Journal of Industrial Technology
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• v.29 no.B
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• pp.101-105
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• 2009

A 1.571GHz LC VCO with optimized spiral inductor for GPS receiver is designed in 130nm CMOS process. The phase noise of the VCO has been reduced the use of high Q inductor and on chip filter. It has phase noise of -91dBc/Hz, -111dBc/Hz, and -131dBc/Hz at 10kHz, 100kHz, and 1MHz offset frequencies from the carrier, respectively. This VCO consumes 2mA from a 0.6V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.10
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• pp.1107-1113
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• 2009

In this paper, the design and implementation of K-Band frequency dividers using 130 nm CMOS process are presented. A Miller frequency divider is presented, which realizes a division range from 20 to 25 GHz with 7.2 mW power consumption from 1.2 V supply. The layout size of the core circuit is about $315{\times}246\;um^2$. In addition, a CML frequency divider which divides the output signal of the Miller frequency divider is also presented, which realizes a division range from 8.5 to 13 GHz with 5.7 mW power consumption. The layout size of the CML core is about $91{\times}98\;um^2$. Cascading the Miller and CML frequency dividers, we confirmed the divide-by-4 operation for the input signal from 20 to 25 GHz.

• Transactions on Electrical and Electronic Materials
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• v.18 no.5
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• pp.257-260
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• 2017

In this paper, we present the design of a 4.5 V low dropout (LDO) voltage regulator implemented in the 130 nm CMOS process. The design uses a two-stage cascaded operational transconductance amplifier (OTA) as an error amplifier, with a body bias technique for reducing dropout voltages. PMOS is used as a pass transistor to ensure stable output voltages. The results show that the proposed LDO regulator has a dropout voltage of 32.06 mV when implemented in the130 nm CMOS process. The power dissipation is only 1.3593 mW and the proposed circuit operates under an input voltage of 5V with an active area of $703{\mu}m^2$, ensuring that the proposed circuit is suitable for low-power applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.370-377
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• 2017

This paper presents a simple noise margin (NM) model of MOS current mode logic (MCML) gates especially in CMOS processes where a large device mismatch deteriorates logic reliability. Trade-offs between speed and logic reliability are discussed, and a simple yet accurate NM equation to capture process-dependent degradation is proposed. The proposed NM equation is verified for 130-nm, 110-nm, 65-nm, and 40-nm CMOS processes and has errors less than 4% for all cases.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.426-432
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• 2012

A fully-integrated low power K-band radar transceiver in 130 nm CMOS process is presented. It consists of a low-noise amplifier (LNA), a down-conversion mixer, a power amplifier (PA), and a frequency synthesizer with injection locked buffer for driving mixer and PA. The receiver front-end provides a conversion gain of 19 dB. The LNA achieves a power gain of 15 dB and noise figure of 5.4 dB, and the PA has an output power of 9 dBm. The phase noise of VCO is -90 dBc/Hz at 1-MHz offset. The total dc power dissipation of the transceiver is 142 mW and the size of the chip is only $1.2{\times}1.4mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.2
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• pp.202-207
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• 2010

In this paper, a novel voltage-controlled oscillator(VCO) using the open loop multiple split ring resonator(OLMSRR) is presented for improving the phase noise, implemented in 130 nm CMOS technology. Compared with the conventional CMOS LC resonator, the proposed CMOS OLMSRR has the larger coupling coefficient value, which makes a higher Q-factor, and has improved the phase noise of the VCO. The proposed CMOS VCO based OLMSRR has the phase noise of -99.67 dBc/Hz @ 1 MHz in the oscillation frequency. Compared with the VCO using the conventional CMOS LC resonator and the proposed VCO using the CMOS OLMSRR structure has been improved in 7 dB. The prototype 24 GHz CMOS VCO is implemented in 130 nm CMOS and occupies a compact die area of $0.7\;mm{\times}0.9\;mm$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.7
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• pp.784-790
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• 2012

In this paper, an all-digital CMOS ultra-wideband(UWB) pulse generator for high band(6~10 GHz) frequency range is presented. The pulse generator is designed and implemented with extremely low power and low complexity. It is designed to meet the FCC spectral mask requirement by using Gaussian pulse shaping circuit and control the center frequency by using CMOS delay line with shunt capacitor. Measurement results show that the center frequency can be controlled from 4.5 GHz to 7.5 GHz and pulse width is 1.5 ns and pulse amplitude is 310 mV peak to peak at 10 MHz pulse repetition frequency(PRF). The circuit is implemented in 0.13 um CMOS process with a core area of only $182{\times}65um^2$ and dissipates the average power of 11.4 mW at an output buffer with 1.5-V supply voltage. However, the core consumes only 0.26 mW except for output buffer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.5
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• pp.682-685
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• 2020

In this paper, we analyze the dominant noise source of conventional inductively degenerated common-source (CS) cascode low noise amplifier (LNA) when width and gate length of stacked transistors vary. Analytical MOSFET and its noise model are used to estimate the contributions of noise sources. All parameters are based on measured data of 60nm, 90nm and 130nm CMOS devices. Based on the noise analysis for different frequencies and device parameters including process nodes, the dominant noise source can be analyzed to optimize noise figure on the configuration. We verified analytically that the intuctively degenerated CS topology can not sustain its benefits in noise above a certain operation frequency of LNA over different process nodes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11A
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• pp.1117-1123
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• 2008

Applications for mobile multimedia are testing the performance limits of present day CPUs with variety. However, hardwired solutions are inflexible and expensive to develop. CPUs with flexibility have limitation of performance. So, the requirement for both ASIC-like performance and CPU-like flexibility has led to reconfigurable processor. Mobile systems require low power and high performance concurrently. In this paper, we propose reconfigurable processor for mobile multimedia with high energy efficiency. Reconfigurable processor with 121MOPS/mW is developed by 130nm CMOS technology. And the processor was simulated for energy efficiency with 539MOPS/mW by 90nm CMOS technology and effective use of instructions. And we tested its applications for multimedia field. We tested the case of inverse MDCT for MP3 and DF for MPEG4 and ME for H.264.