• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.469-471
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• 2008

The charge pump affects the performance of PLL. In designing the charge pump, we need to consider various issues such as current mismatch, charge sharing, feedthrough, charge injection, and leakage current. This paper propose the new charge pump circuit which is improved in terms of the current match over the existing high-speed charge pump. The simple method used for reducing current mismatch is the technique that uses a cascode in order to increase the output resistance of the charge pump. However the method limits the output voltage range of the charge pump. So the method is hard to apply as the supply voltage is lowered. Thus this paper proposes a new charge pump circuit using an op amp instead of the cascode. And the new charge pump circuit has an excellent current matching characteristics over a wide output range.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.5
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• pp.37-42
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• 2012

In this paper, a new charge pump is proposed to reduce the timing mismatch in the conventional current-steering charge pumps. Conventional current-steering charge pumps used NMOS input stages both for UP and DOWN signals, which resulted in different numbers of stage for UP and DOWN delay paths. The proposed charge pump has equalized the numbers of stages for UP and DOWN signals by using a PMOS stage for the DOWN signal. The simulation results show that the conventional current-steering charge pump has 14ns and 6ns for optimized timing mismatches between UP and DOWN signals for turn-on and turn-off, respectively. On the other hand, the proposed charge pump has improved timing mismatches of 6ns and 5ns for turn-on and turn-off, respectively. As a result, the reference spurs are reduced from -26dBc to -39dBc for the proposed charge pump. The proposed charge pump was designed by using $0.18{\mu}m$ CMOS technology. The measurement results show that the maximum variation of the charging and discharging current over the charge pump output voltage range of 0.3~1.5V is approximately 1.5%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2495-2502
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• 2012

This paper presents a new structure of phase looked loop (PLL) for replacing a process sensitive resistor in loop filter with an additional charge pump (CP). The additional charge pump works as a resistor in a loop filter. The output of two charge pumps changes same direction according to process variation. The simulation results according to process conditions(SS/TT/FF) demonstrate that the proposed PLL works properly with process variations. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process and proved by simulation with HSPICE.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.80-86
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• 2009

In this paper, we present a new charge pump circuit feasible for the implementation with standard twin-well CMOS process technology. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned on during each half of clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. The performance comparison by simulations and measurements demonstrates that the proposed charge pump exhibits the higher output voltage, the larger output current and a better power efficiency over the traditional twin-well charge pumps.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2380-2386
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• 2013

A PLL with an unipolar charge pump and a loop filter consisting of sample-hold capacitor and 2nd-order RC filter has been proposed. The goal of the proposed PLL is the suppression of reference spur which is caused by charge pump mismatch. It also improves phase noise characteristic. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.137-145
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• 2008

In this paper, novel CMOS charge pump having NMOS and PMOS transfer switches and a bulk-pumping circuit has been proposed. The NMOS and PMOS transfer switches allow the charge pump to improve the current-driving capability at the output. The bulk-pumping circuit effectively solves the bulk forward problem of the charge pump. To verify the effectiveness, the proposed charge pump was designed using a 80-nm CMOS process. The comparison results indicate that the proposed charge pump enhances the current-driving capability by more than 47% with pumping speed improved by 9%, as compared to conventional charge pumps having either NMOS or PMOS transfer switch. They also indicate that the charge pump reduces the worst-case forward bias of p-type bulk by more than 24%, effectively solving the forward current problem.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.10
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• pp.1899-1909
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• 2007

A cross-coupled charge pump with internal pumping capacitor, witch is advantages from a point of minimizing TFT-LCD driver IC module, is newly proposed in this paper. By using a NMOS and a PMOS diode connected to boosting node from VIN node, the pumping node is precharged to the same value each pumping node at start pumping operation. Since the lust-stage charge pump is designed differently from the other stage pumps, a back current of pumped charge from charge pumping node to input stage is prevented. As a pumping clock driver is located the font side of pumping capacitor, the driving capacity is improved by reducing a voltage drop of the pumping clock line from parasitic resistor. Finally, a layout area is decreased more compared with conventional cross-coupled charge pump by using a stack-MIM capacitors. A proposed charge pump for TFT-LCD driver IC is designed with $0.13{\mu}m$ triple-well DDI process, fabricated, and tested.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1266-1274
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• 2006

A non-overlap boosted-clock charge pump(NBCCP) with internal pumping capacitor, an advantageous circuit from a minimizing point of TFT-LCD driver IC module, is proposed in this paper. By using the non-overlap boosted-clock swinging in 2VDC voltage, the number of pumping stages is reduced to half and a back current of pumping charge from charge pumping node to input stage is also prevented compared with conventional cross-coupled charge pump with internal pumping capacitor. As a result, pumping current of the proposed NBCCP circuit is increased more than conventional cross-coupled charge pump, and a layout area is decreased. A proposed DC-DC converter for TFT-LCD driver IC is designed with $0.18{\mu}m$ triple-well CMOS process and a test chip is in the marking.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.74-80
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• 2006

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise performance. The proposed PLL has two Charge Pump (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppress the voltage fluctuation of LF. In result, it improves phase noise characteristic. The Proposed PLL has been fabricated with 0.35fm 3.3V CMOS process. Measured phase noise at 1-MHz offset is -103dBc/Hz resulting in a minimum 3dBc/Hz phase noise improvement compared to the conventional PLL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.94-99
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• 2010

This paper presents a charge pump architecture for correcting the current mismatch due to the PVT variation. In general, the current mismatch of the charge pump should be minimized to improve the phase noise and spur performance of the PLL. In order to correct the current mismatch of the charge pump, the current difference is detected by the replica charge pump and fed back into the main charge pump. This scheme is very simple and guarantees the high accuracy compared with the prior works. Also, it shows a good dynamic performance because the mismatch is corrected continuously. It is implemented in 0.13um CMOS process and the die area is $100{\mu}m\;{\times}\;160{\mu}m$. The voltage swing is from 0.2V to 1V at supply voltage of 1.2V. The charging and discharging currents are $100{\mu}A$, respectively and the current mismatch due to the PVT variation is less than 1%.