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A Low Phase Noise Phase Locked Loop with Current Compensating Scheme  

Song, Youn-Gui (Division of Electronics, Computer and Telecommunication Engineering, Pukyong National University)
Choi, Young-Shig (Division of Electronics, Computer and Telecommunication Engineering, Pukyong National University)
Ryu, Ji-Goo (Division of Electronics, Computer and Telecommunication Engineering, Pukyong National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.12, 2006 , pp. 74-80 More about this Journal
Abstract
This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise performance. The proposed PLL has two Charge Pump (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppress the voltage fluctuation of LF. In result, it improves phase noise characteristic. The Proposed PLL has been fabricated with 0.35fm 3.3V CMOS process. Measured phase noise at 1-MHz offset is -103dBc/Hz resulting in a minimum 3dBc/Hz phase noise improvement compared to the conventional PLL.
Keywords
PLL; voltage controlled resistor; current compensation; adaptive bandwidth;
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