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A Charge Pump with Matched Delay Paths for Reduced Timing Mismatch  

Heo, Joo-Il (Chonbuk National University)
Heo, Jung (Chonbuk National University)
Jeong, Hang-Geun (Chonbuk National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.49, no.5, 2012 , pp. 37-42 More about this Journal
Abstract
In this paper, a new charge pump is proposed to reduce the timing mismatch in the conventional current-steering charge pumps. Conventional current-steering charge pumps used NMOS input stages both for UP and DOWN signals, which resulted in different numbers of stage for UP and DOWN delay paths. The proposed charge pump has equalized the numbers of stages for UP and DOWN signals by using a PMOS stage for the DOWN signal. The simulation results show that the conventional current-steering charge pump has 14ns and 6ns for optimized timing mismatches between UP and DOWN signals for turn-on and turn-off, respectively. On the other hand, the proposed charge pump has improved timing mismatches of 6ns and 5ns for turn-on and turn-off, respectively. As a result, the reference spurs are reduced from -26dBc to -39dBc for the proposed charge pump. The proposed charge pump was designed by using $0.18{\mu}m$ CMOS technology. The measurement results show that the maximum variation of the charging and discharging current over the charge pump output voltage range of 0.3~1.5V is approximately 1.5%.
Keywords
PLL; Charge Pump; Timing Mismatch; Current Mismatch;
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