Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Complementary Dual-Path Charge Pump with High Pumping Efficiency in Standard CMOS Logic Technology

상보형 전하이동 경로를 갖는 표준 CMOS 로직 공정용 고효율 전하펌프 회로

  • Lee, Jung-Chan (School of Electrical Engineering and Computer Science, Kyungpook National University) ;
  • Chung, Yeon-Bae (School of Electrical Engineering and Computer Science, Kyungpook National University)
  • 이정찬 (경북대학교 전자전기컴퓨터학부) ;
  • 정연배 (경북대학교 전자전기컴퓨터학부)
  • Published : 2009.12.25
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Abstract

In this paper, we present a new charge pump circuit feasible for the implementation with standard twin-well CMOS process technology. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned on during each half of clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. The performance comparison by simulations and measurements demonstrates that the proposed charge pump exhibits the higher output voltage, the larger output current and a better power efficiency over the traditional twin-well charge pumps.

전하펌프의 성능은 공급전압에 의해 크게 영향을 받는다. 본 논문에서는 표준 twin-well CMOS 로직 공정으로 제작 가능하며, 낮은 공급전압에서도 높은 효율을 갖는 새로운 전하펌프 회로를 제안하고 검증하였다. 제안한 전하펌프는 이중의 전하 전달 경로와 간단한 2-phase 클락을 사용한다. 한 주기의 펌핑 사이클 동안 각 펌핑 단에서 입력전압을 2배로 승압하며, 상보적으로 연결된 PMOS 트랜지스터를 전달 스위치로 사용하여 트랜지스터의 문턱전압에 의한 전압강하 없이 승압된 전압을 다음 승압 단으로 전달한다. 시뮬레이션과 측정을 통해 제안한 전하펌프를 검증하였으며, 동일한 공정조건에서 제작 가능한 기존 전하펌프들 보다 높은 출력전압과 큰 전류 구동능력 그리고 더 높은 전력효율을 가진다는 것을 확인하였다.

Keywords

References

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