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Complementary Dual-Path Charge Pump with High Pumping Efficiency in Standard CMOS Logic Technology  

Lee, Jung-Chan (School of Electrical Engineering and Computer Science, Kyungpook National University)
Chung, Yeon-Bae (School of Electrical Engineering and Computer Science, Kyungpook National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.12, 2009 , pp. 80-86 More about this Journal
Abstract
In this paper, we present a new charge pump circuit feasible for the implementation with standard twin-well CMOS process technology. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned on during each half of clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. The performance comparison by simulations and measurements demonstrates that the proposed charge pump exhibits the higher output voltage, the larger output current and a better power efficiency over the traditional twin-well charge pumps.
Keywords
charge pump; dual charge-transfer path; two-phase clock; twin-well CMOS technology;
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1 S. Kobayashi, M. Mihara, Y. Miyawaki, M. Ishii, T. Futatsuya, A. Hosogane, A. Ohba, Y. Terada, N. Ajika, Y. Kunori, K. Yuzuriha, M. Hatanaka, H. Miyoshi, T. Y oshihara, Y. Uji, A. Matsuo, Y. Taniguchi, and Y. Kiguchi, "A 3.3V -only 16 Mb DINOR flash memory," in Proc. of IEEE International Solid-Stage Circuits Conf., pp. 122-123, 1995
2 T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE Journal of Solid-State Circuits, Vol. 30, No.3, pp. 166-172, March 1995   DOI   ScienceOn
3 T. A. F. Duisters and E. C. Dijkmans, "A -go-dB THD rail-to-rail input Opamp using a new local charge pump in CMOS," IEEE Journal of Solid-State Circuits, Vol. 33, No.7, pp. 947-955, July 1998   DOI   ScienceOn
4 K. -H. Choi, J. -M. Park, J. -K. Kim, T. -S. Jung, and K. -D. Suh, "Floating-well charge pump circuits for sub-2.0V single power supply flash memories," in Proc. of Symposium on VLSI Circuits, pp. 61-62, 1997
5 R. Pelliconi, D. Iezzi, A. Baroni, M. Pasotti, and P. L. Rolandi, "Power efficient charge pump in deep submicron standard CMOS technology," IEEE Journal Solid-State Circuits, Vol. 38, No. 6, pp. 1068-1071, June 2003   DOI   ScienceOn
6 A. Richelli, L. Mensi, L. Colalongo, P. L. (1082) Rolandi, and Z. M. Kov$\acute{a}$cs-Vajna, "A 1.2-to-8V charge-pump with improved power efficiency for non-volatile memories," in Proc. of IEEE International Solid-State Circuits Conf., pp. 522-523, 2007
7 J. F. Dickson, "On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique," IEEE Journal of Solid-State Circuits, Vol. SC-11, No.3, pp. 374-378, June 1976
8 J. Lee, H. -S. Im, D. -S. Byeon, K. -H. Lee, D. -H. Chae, K. -H. Lee, S. W. Hwang, S. -S. Lee, Y. -H. Lim, J. -D. Lee, J. -D. Choi, Y. -I. Seo, J. -S. Lee, and K. -D. Suh, "High-performance 1-Gb NAND flash memory with 0.12-$\mu$m technology," IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, pp. 1502-1509, November 2002   DOI   ScienceOn
9 C. Lauterbach, W. Weber, and D. Romer, "Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps," IEEE Journal of Solid-State Circuits, Vol. 35, No.5, pp. 719-723, May 2000   DOI   ScienceOn
10 J. Shin, I. - Y. Chung, Y. J. Park, and H. S. Min, "A new charge pump without degradation in threshold voltage due to body effect," IEEE Journal of Solid-State Circuits, Vol. 35, No.8, pp. 1227-1230, August 2000   DOI   ScienceOn