• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2000.10a
• /
• pp.480-484
• /
• 2000

The channel length influence of n-channel Si-based FETs is investigated by computer simulation. Using a two-dimensional hydrodynamic model, devices having various gate length are examined. We have observed the characteristics of LDD model of MOSFET by investigating of their current, voltage, electric field and impact ionization. These devices are scaled using various factors. We have analyzed I-V characteristics and the effect of impact ionization according to channel length.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.6 no.4
• /
• pp.545-552
• /
• 2011

In this article, reference voltages in a general flash ADC are not obtained from a series of resistors but floating gates. When a behavior model simulation was performed in a pipelined ADC including the suggested flash ADC as a result of an ADC's overall function, it showed results that SNR is approximately 77 dB and resolution is 12 bit. And more than almost 90% showed INL within ${\pm}0.5$ LSB, and like INL, more than 90% showed DNL within ${\pm}0.5$ LSB.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.4
• /
• pp.1-6
• /
• 2012

This paper presents the extraction and analysis of small-signal parameters of tunneling field-effect transistors (TFETs) by using TCAD device simulation. The channel lengths ($L_G$) of the simulated devices varies from 50 nm to 100 nm. The parameter extraction for TFETs have been performed by quasi-static small-signal model of conventional MOSFETs. The small-signal parameters of TFETs with different channel lengths were extracted according to gate bias voltage. The $L_G$-dependency of the effective gate resistance, transconductance, source-drain conductance, and gate capacitance are different with those of conventional MOSFET. The $f_T$ of TFETs is inverely proportional not to $L_G{^2}$ but to $L_G$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.4
• /
• pp.49-56
• /
• 2008

This paper introduces a compact analytical current conduction model of long-channel depletion-mode n-type nanowire field-effect transistors (NWFETs). The NWFET used in this work was fabricated with the bottom-up process and it has a bottom-gate structure. The model includes all current conduction mechanisms of the NWFET operating at various bias conditions. The results simulated from the newly developed NWFET model reproduce a reported experimental results within a 10% error.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.12
• /
• pp.194-200
• /
• 2012

In this paper, we proposed a SPICE model of high-voltage insulated gate bipolar transistor(IGBT). The proposed model consists of two sub-devices, a MOSFET and a BJT. Basic I-V characteristics and their temperature dependency were realized by adjusting various parameters of the MOSFET and the BJT. To model nonlinear parasitic capacitances such as a reverse-transfer capacitance, multiple junction diodes, ideal voltage and current amplifiers, a voltage-controlled resistor, and passive devices were added in the model. The accuracy of the proposed model was verified by comparing the simulation results with the experimental results of a 1200V trench gate IGBT.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.7
• /
• pp.464-472
• /
• 2001

Asymmetric n-MOSFET＇s for improving packing density have been fabricated with 0.35 ${\mu}{\textrm}{m}$ CMOS process. Electrical characteristics of asymmetric n-MOSFET show a lower saturation drain current and a higher linear resistance compared to those of symmetric devices. Substrate current of asymmetric MOSFET is lower than that of symmetric devices. Asymmetric n-MOSFET＇s have been modeled using a parasitic resistance associated with abnormally structured drain or source and a conventional n-MOSFET model. MEDICI simulation has been done for accuracy of this modeling. Simulated values of reverse as we11 as forward saturation drain current show good agreement with measured values for asymmetric device.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.3
• /
• pp.15-30
• /
• 2004

In this paper, an analytical modeling for the dark and photo-current characteristics of a buried-gate short- channel GaAs MESFET is presented. The presented model shows that the increase of drain current under illumination is largely due to not the increase of photo-conductivity in the neutral region but the narrowing effect of the depletion layer width. The carrier density profile within the neutral region is derived from solving the carrier continuity equation one-dimensionally. In deriving the photo-generated current, we assume that the photo-current is compensated with the thermionic emission current at the gate-channel interface. Moreover, the two-dimensional Poisson's equation is solved by taking into account the drain-induced longitudinal field effect. In conclusion, the proposed model seems to provide a reasonable explanation for the dark and photo current characteristics in a unified manner.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.3
• /
• pp.570-576
• /
• 2007

In this study, the characteristics of metal-ferroelectric-semiconductor FET (MFSFET) device is investigated using field-dependent polarization and square-law FET models. From drain current with the gate voltage variation, when coercive voltages of ferroelectric thin film are 0.5 and 1V, the memory windows are 1 and 2V, respectively. When the gate voltages are 0, 0.1, 0.2 and 0.3V, the difference of saturation drain currents of the MFSFET device at two threshold voltages in ID-VD curve are 1.5, 2.7, 4.0, and 5.7mA, respectively. As a result of the analysis for drain currents after tine lapse, which is based on the simulation for hysteresis loop and the fitting of retention properties of ferroelectric thin films such as PLZT(10/30/70), PLT(10) and PZT(30/70) thin film shows excellent reliability that the decrease of saturation current is about 18% after 10 years.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.6
• /
• pp.1-7
• /
• 2004

We performed two-dimensional (20) computer-based modeling and simulation of FinFET by solving the coupled Poisson-Schrodinger equations quantum-mechanically in a self-consistent manner. The simulation results are carefully investigated for FinFET with gate length(Lg) varying from 10 to 80nm and with a Si-fin thickness($T_{fin}$) varying from 10 to 40nm. Current-voltage (I-V) characteristics are compared with the experimental data. Device optimization has been performed in order to suppress the short-channel effects (SCEs) including the sub-threshold swing, threshold voltage roll-off, drain induced barrier lowering (DIBL). The quantum-mechanical simulation is compared with the classical appmach in order to understand the influence of the electron confinement effect. Simulation results indicated that the FinFET is a promising structure to suppress the SCEs and the quantum-mechanical simulation is essential for applying nano-scale device structure.

• Review of KIISC
• /
• v.16 no.3
• /
• pp.25-33
• /
• 2006

본 논문에서는 임베디드 시스템 온칩 적용을 위한 통합 보안 프로세서를 SIP(Semiconductor Intellectual Property)로 설계하였다. 각각의 SIP는 VHDL RTL로 모델링하였으며, 논리합성, 시뮬레이션, FPGA 검증을 통해 재사용이 가능하도록 구현하였다. 또한 ARM9과 SIP들이 서로 통신이 가능하도록 AMBA AHB의 스펙에 따라 버스동작모델을 설계, 검증하였다. 플랫폼기반의 통합 보안 SIP는 ECC, AES, MD-5가 내부 코어를 이루고 있으며 각각의 SIP들은 ARM9과 100만 게이트 FPGA가 내장된 디바이스를 사용하여 검증하였으며 최종적으로 매그나칩 $0.25{\mu}m(4.7mm\times4.7mm)$ CMOS 공정을 사용하여 MPW(Multi-Project Wafer) 칩으로 제작하였다.