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Current Conduction Model of Depletion-Mode N-type Nanowire Field-Effect Transistors (NWFETS)  

Yu, Yun-Seop (Department of Information & Control Engineering and Electronic Technology Institute, Hankyong National University)
Kim, Han-Jung (Department of Information & Control Engineering and Electronic Technology Institute, Hankyong National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.4, 2008 , pp. 49-56 More about this Journal
Abstract
This paper introduces a compact analytical current conduction model of long-channel depletion-mode n-type nanowire field-effect transistors (NWFETs). The NWFET used in this work was fabricated with the bottom-up process and it has a bottom-gate structure. The model includes all current conduction mechanisms of the NWFET operating at various bias conditions. The results simulated from the newly developed NWFET model reproduce a reported experimental results within a 10% error.
Keywords
Nanowire field-effect transistor(NWFET); Depletion-mode; Current conduction; Pinch-off; Surface depletion effects; Circuit simulation;
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1 A. Star, J.-C. P. Gabriel, K. Bradley, and G. Gruner, "Electronic detection of specific protein binding using nanotube FET devices", Nano Lett., Vol. 3, pp. 459-463, 2003   DOI   ScienceOn
2 S. Han, W. Jin, D. Zhang, T. Tang, C. Li, X. Liu, Z. Liu, B. Lei, and C. Zhou, "Photoconduction studies on GaN nanowire transistors under UV and polarized UV illumination", Chem. Phys. Lett., Vol. 389, pp. 176-180, 2004   DOI   ScienceOn
3 V. Schmidt, H. Riel, S. Senz, S. Karg, W. Riess, U. Gosele, "Realization of a Silicon Nanowire Vertical Surround-Gate Field-Effect Transistor", Small, Vol. 2, pp. 85-88, 2006   DOI   ScienceOn
4 T. L. Wade, X. Hoffer, A. D. Mohammed, J.-F. Dayen, D. Pribat, and J.-E. Wegrowe, "Nanoporous alumina wire templates for surrounding-gate nanowire transistors", Nanotechnology, Vol. 18, pp. 125201-125204, 2007   DOI   ScienceOn
5 D. Wang, Q. Wang, A. Javey, R. Tu, H. Dai, H. Kim, P. C. Mclntyre, T. Krishnamohan and K. C. Saraswat, "Germanium nanowire field-effect transistors with $SiO_2$ and high-$HfO_2$ gate dielectrics", Appl. Phys. Lett., Vol. 83, pp. 2432-2434, 2003   DOI   ScienceOn
6 H.-Y. Cha, H. Wu, M. Chandrashekhar, Y. C. Choi, S. Chae, G. Koley and M. G. Spencer, "Fabrication and characterization of pre-aligned gallium nitride nanowire field-effect transistors", Nanotechnology, Vol. 17, pp. 1264-1271, 2006   DOI   ScienceOn
7 Y. G. Chen, S. Y. Ma, J. B. Kuo, Z. Yu, and R. W. Dutton, "An analytical drain current model considering both electron and lattice temperatures simultaneously for deep submicron ultrathin SOI NMOS devices with self-heating", IEEE Trans. Electron Devices, Vol. 42, pp. 899-906, 1995   DOI   ScienceOn
8 P. Antognetti, D. D. Caviglia, and E. Profumo, "CAD model for threshold and subthreshold conduction in MNOSFETs", IEEE J. Solid-State Circuits, Vol. SSC-17, pp. 454-458, 1982
9 S. Datta, "Nanoscale device modeling: The Green's function method", Superlattices and Microstructures, Vol. 28, pp. 253, 2000   DOI   ScienceOn
10 Y. W. Heo, L. C. Tien, Y. Kwon, D. P. Norton, S. J. Pearton, B. S. Kang, and F. Ren, "Depletion-mode ZnO nanowire field-effect transistor", Appl. Phys. Lett., Vol. 85, pp. 2274-2276, 2004   DOI   ScienceOn
11 M. Shin, "Quantum simulation of device characteristics of silicon nanowire FETs," IEEE Trans. Nanotechnology, vol. 6, pp. 230-237, 2007   DOI   ScienceOn
12 C. Y. Yim, D. Y. Jeon, K. H. Kim, G. T. Ki, Y. S. Woo, S. Roth, J. S. Lee, and S. Kim, "Electrical Properties of the ZnO Nanowire Transistor and its Analysis with Equivalent Circuit Model", J. Kor. Phys. Soc., Vol. 48, pp. 1565-1569, 2006
13 T. Bryllert, L. Wernersson, T. Lowgren and L. Samuelson, "Vertical wrap-gated nanowire transitors", Nanotechnology, Vol. 17, pp. S227-S230, 2006   DOI   ScienceOn
14 D. M. Caughey and R. E. Thomas, "Carrier mobilities in silicon empirically related to doping and field", in Proc. IEEE, Vol. 55, pp. 2192-2193, 1967   DOI   ScienceOn
15 J. Wang, E. Polizzi, and M. Lundstrom, "A three-dimensional quantum simulation of silicon nanowire transistors with the effective-mass approximation", J. Appl. Phys., Vol. 96, pp. 2192-2203, 2004   DOI   ScienceOn
16 J.-P. Colinge, "Conduction Mechanism in Thin-Film Accumulation-Mode SOI p-Channel MOSFET's", IEEE Trans. Electron Devices, Vol. 37, pp. 718-723, 1990   DOI   ScienceOn
17 S.-M. Koo, M. D. Edelstein, Q. Li, C. A. Richter, and E. M. Vogel, "Silicon nanowires as enhancement-mode Schottky barrier field-effect transistors", Nanotechnology, Vol. 16, pp. 1482-1485, 2006   DOI   ScienceOn
18 W. I. Park, J. S. Kim, G.-C. Yi, M. H. Bae and H.-J. Lee, "Fabrication and electrical characteristics of high-performance ZnO nanorod field-effect transistors", Appl. Phys. Lett., Vol. 85, pp. 5052-5054, 2004   DOI   ScienceOn
19 Y. Li, F. Qian, J. Xiang, and C. M. Lieber, "Nanowire electronic and optoelectronic devices", Materials Today, vol. 9, pp. 18-27, 2006
20 J. Xiang, W. Lu, Y. Hu, Y. Wu, H. Yan, and C. M. Lieber, "Ge/Si nanowire heterostructures as high-performance field-effect transistors", Nature, Vol. 441, pp. 489-493, 2006   DOI   ScienceOn