1 |
A. S. Verhulst, W. G. Vandenberghe, K Maex, and G. Groeseneken, "Tunnel Field-Effect Transistor without Gate-Drain Overlap," Applied Physics Lett., vol. 91, pp. 053102-1-053102-3, 2007.
DOI
ScienceOn
|
2 |
J. Jin, J.-J. Ou, C.-H. Chen, W. Liu, M. J. Deen, P. R. Gray, and C. Hu, "An Effective Gate Resistance Model for CMOS RF and Noise Modeling," 1998 International Electron Device Meeting, pp. 35.5.1-35.5.4, 1998.
|
3 |
K. K. Bhuwalka, J. Schulze, and I. Eisele, "Scaling the Vertical Tunnel FET With Tunnel Bandgap Modulation and Gate Workfunction Engineering," IEEE Trans. Electron Devices, vol. 52, no. 5, pp. 909-917, May 2005.
DOI
ScienceOn
|
4 |
K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
|
5 |
윤형선, 임수, 안정호, 이희덕, "RFIC를 위한 Nano-scale MOSFET의 Effective gate resistance 특성 분석", 대한전자공학회논문지 제 41 권 SD 편11 호 pp. 1-6, 2004.
|
6 |
이병진, 박성욱, 엄우용, "SOI FinFET's의 소신호 등가 모델과 변수 추출", 대한전자공학회논문지 제 44 권 IE 편 제 2 호 pp. 1-7, 2007.
|
7 |
N.-K. Tak and J.-H. Lee, "RF Small Signal Modeling of Tri-Gate MOSFETs Implemented on Bulk Si Wafers", 2004 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, pp. 266-269, 2004.
|
8 |
In Man Kang and Hyungcheol Shin, "Non-Quasi-Static Small-Signal Modeling and Analytical Parameter Extraction of SOI FinFETs," IEEE Trans. Nanotechnol., vol.5, no. 3, pp. 205-210, May 2006.
DOI
|
9 |
Y. Yang, X. Tong, L.-T. Yang, P.-F. Guo, L. Fan, and Y.-C. Yeo, "Tunneling field-effect transistor: Capacitance components and modeling," IEEE Electron Device Lett., vol. 31, no. 7, pp. 752-754, Jul. 2010.
DOI
|
10 |
W. Y. Choi and W. Lee, "Hetero-gate-dielectric tunneling field-effect transistors," IEEE Trans. Electron Devices, vol. 57, no. 9, pp. 2317-2319, Sep. 2010.
|