Yu, Hyun Kyu;Kwon, Sang Jik;Lee, Joong Whan;Kwon, Oh Joon;Kang, Young Il
758
The design, fabrication and performance of vertical double diffused power MOSFET (VDMOS) were described. On the antimony (Sb) doped (~7x10**17 cm**-3) silicon substrate (N+), epitaxial layer(N-) was grown. The thickness and the resistivity of this layer were 32\ulcorner and about 12\ulcorner-cm, respectively. The P- channel length which was controlled by sequential P-/N+ double diffuison method was about 1~2 \ulcorner, and was processed with the self alignment of 21 \ulcorner width poly silicon. To improve the breakdown voltage with constant on-resistance (Ron) about 1\ulcorner, three P+ guard rings were laid out around main pattern. With chip size of 4800\ulcorner x4840 \ulcorner, the VDMOS has shown breakdown voltage of 410~440V, on-resistance within 1.0~1.2\ulcornerand the current capablity of more than 5A.