• Title/Summary/Keyword: testability

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A New RF Test Circuit on a DFT Technique (DFT 방법을 위한 새로운 고주파 검사 회로)

  • Ryu Jee-Youl;Noh Seok-Ho
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2006.05a
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    • pp.902-905
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    • 2006
  • This paper presents a new RF testing scheme based on a design-for-testability (DFT) method for measuring functional specifications of RF integrated circuits (IC). The proposed method provides input impedance. gain, noise figure. input voltage standing wave ratio (VSWR) and output signal-to-noise ratio (SNR) of a low noise amplifier (LNA). The RF test scheme is based on theoretical expressions that produce the actual RF device specifications by output DC voltages from the DR chip.

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ALU Design & Test for 32-bit DSP RISC Processors (32비트 DSP RISC 프로세서를 위한 ALU 설계 및 테스트)

  • 최대봉;문병인
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.1169-1172
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    • 1998
  • We designed an ALU(Airthmetic Logic Unit) with BIST(Built-In Self Test), which is suitable for 32-bit DSP RISC processors. We minimized the area of this ALU by allowing different operations to share several hardware blocks. Moreover, we applied DFT(Design for Testability) to ALU and offered Bist(Built-In Self-Test) function. BIST is composed of pattern generation and response analysis. We used the reseeding method and testability design for the high fault coverage. These techniques reduce the test length. Chip's reliability is improved by testing and the cost of testing system can be reduced.

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Synthesis for Testability by Adding Transitions of Undefined States to State Transition Tables

  • Yotsuyanagi, Hiroyuki;Hashizume, Masaki;Tamesada, Takeomi
    • Proceedings of the IEEK Conference
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    • 2000.07a
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    • pp.355-358
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    • 2000
  • In this paper we propose procedures to enhance testability by modifying state transition tables. In these procedures, transitions about undefined states, which are not described in state transition tables but exist in a synthesized gate level circuit, are added to a state transition table. Experimental results for MCNC benchmarks are shown.

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A Design and Implementation of Wrapper for Improving Component Testability (컴포넌트의 테스트가능성 향상을 위한 래퍼 설계와 구현)

  • 송호진;최은만
    • Proceedings of the Korean Information Science Society Conference
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    • 2003.10b
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    • pp.340-342
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    • 2003
  • 컴포넌트는 서드파티(third-party)소스코드 형태로 배포되지 않는 등 여러 가지 요인으로 인해 테스트가능성(testability)이 낮아지게 된다. 이렇게 낮은 테스트가능성으로 인하여 개발된 컴포넌트가 실제로 재사용되었을 때 테스트에 많은 어려움이 따르게 된다. 이러한 테스트가능성을 향상시키기 위한 방법으로서 컴포넌트에 테스트를 위한 래퍼(wrapper)를 적용할 수 있다. 본 연구에서는 테스트가능성을 향상시키기 위한 방법인 래퍼를 설계하고 구현하는 방법에 대한 연구를 수행하였다.

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Disign Technique and Testability Analysis of High Speed Full-Swing BiCMOS Circuits (테스트가 용이한 고속 풀 스윙 BiCMOS회로의 설계방식과 테스트 용이도 분석)

  • Lee, Jae Min;Jung, Kwang Sun
    • Journal of the Korean Society of Industry Convergence
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    • v.4 no.2
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    • pp.199-205
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    • 2001
  • With the growth of BiCMOS technology in ASIC design, the issue of analyzing fault characteristics and testing techniques for BiCMOS circuits become more important In this paper, we analyze the fault models and characteristics of high speed full-swing BiCMOS circuits and the DFT technique to enhance the testability of full-swing high speed BiCMOS circuits is discussed. The SPICE simulation is used to analyze faults characteristics and to confirm the validity of DFT technique.

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A New Logic Transformation Method for Both Low Power and High Testability (저 전력소모와 높은 테스트용이성을 위한 새로운 논리 변환 방법)

  • 손윤식;정정화
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.9
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    • pp.692-701
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    • 2003
  • In this paper, a new logic transformation method to consider both low power consumption and high testability is proposed. We search the CFF(Compact Fanout Free) that has low probability of being observable at the primary outputs. Under the condition that the CFF is unobservable at all primary outputs, the switching operations in it can be removed by adding redundant connections into it. The testability of the transformed circuit generally tends to reduce. In our method, however, the inserted redundant connections operate as test points in the test mode and can improve not only the controllability but also the observability of the CFF. The transformed circuit consumes less power in the normal mode and also has higher testability in the test mode. To show the efficiency of the proposed logic transformation method, we perform some experiments on the MCNC benchmark test circuits. The results show that the power consumption of the transformed circuit is reduced by 13% maximally and the fault coverage of the transformed circuit is increased.

On-Chip Design-for-Testability Circuit for RF System-On-Chip Applications (고주파 시스템 온 칩 응용을 위한 온 칩 검사 대응 설계 회로)

  • Ryu, Jee-Youl;Noh, Seok-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.3
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    • pp.632-638
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    • 2011
  • This paper presents on-chip Design-for-Testability (DFT) circuit for radio frequency System-on-Chip (SoC) applications. The proposed circuit measures functional specifications of RF integrated circuits such as input impedance, gain, noise figure, input voltage standing wave ratio (VSWRin) and output signal-to-noise ratio (SNRout) without any expensive external equipment. The RF DFT scheme is based on developed theoretical expressions that produce the actual RF device specifications by output DC voltages from the DFT chip. The proposed DFT showed deviation of less than 2% as compared to expensive external equipment measurement. It is expected that this circuit can save marginally failing chips in the production testing as well as in the RF system; hence, saving tremendous amount of revenue for unnecessary device replacements.

An Non-Scan DFT Scheme for RTL Circuit Datapath (RTL 회로의 데이터패스를 위한 비주사 DFT 기법)

  • Chang, Hoon;Yang, Sun-Woong;Park, Jae-Heung;Kim, Moon-Joon;Shim, Jae-Hun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.2
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    • pp.55-65
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    • 2004
  • In this paper, An efficient non-scan DFT method for datapaths described in RTL is proposed. The proposed non-scan DFT method improves testability of datapaths based on hierarchical testability analysis regardless to width of the datapath. It always guarantees higher fault efficiency and faster test pattern generation time with little hardware overhead than previous methods. The experimental result shows the superiority of the proposed method of test pattern generation time, application time, and area overhead compared to the scan method.

A New Design-for-Testability Circuit for Low Noise Amplifiers (저잡음 증폭기를 위한 새로운 구조의 검사용 설계회로)

  • Ryu Jee-Youl;Noh Seok-Ho
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.3 s.345
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    • pp.68-77
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    • 2006
  • This paper presents a new Design-for-Testability (DfT) circuit for 4.5-5.5GHz low noise amplifiers (LNAs). The DfT circuit measures gain, noise figure, input impedance, input return loss, and output signal-to-noise ratio for the LNA without external expensive equipment. The DfT circuit is designed using 0.18m SiGe technology. The circuit utilizes input impedance matching and DC output voltage measurements. The technique is simple and inexpensive.

An Effective Multiple Transition Pattern Generation Method for Signal Integrity Test on Interconnections (Signal Integrity 연결선 테스트용 다중천이 패턴 생성방안)

  • Kim, Yong-Joon;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.10
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    • pp.39-44
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    • 2008
  • Scan architecture is very effective design-for-testability technique that is widely used for high testability, however, it requires so much test time due to test vector shifting time. In this paper, an efficient scan test method is presented that is based on the Illinois scan architecture. The proposed method maximizes the common input effect via a scan chain selection scheme. Experimental results show the proposed method requires very short test time and small data volume by increasing the efficiency of common input effect.