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A New Design-for-Testability Circuit for Low Noise Amplifiers  

Ryu Jee-Youl (Department of Electrical Engineering, Arizona State University)
Noh Seok-Ho (Major of Electronic Engineering, College of Electronic & Information Engineering, Andong National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea TC / v.43, no.3, 2006 , pp. 68-77 More about this Journal
Abstract
This paper presents a new Design-for-Testability (DfT) circuit for 4.5-5.5GHz low noise amplifiers (LNAs). The DfT circuit measures gain, noise figure, input impedance, input return loss, and output signal-to-noise ratio for the LNA without external expensive equipment. The DfT circuit is designed using 0.18m SiGe technology. The circuit utilizes input impedance matching and DC output voltage measurements. The technique is simple and inexpensive.
Keywords
DfT circuit; LNA; RFIC Chip;
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