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http://dx.doi.org/10.6109/jkiice.2011.15.3.632

On-Chip Design-for-Testability Circuit for RF System-On-Chip Applications  

Ryu, Jee-Youl (부경대학교 정보통신공학과)
Noh, Seok-Ho (안동대학교 전자공학과)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.15, no.3, 2011 , pp. 632-638 More about this Journal
Abstract
This paper presents on-chip Design-for-Testability (DFT) circuit for radio frequency System-on-Chip (SoC) applications. The proposed circuit measures functional specifications of RF integrated circuits such as input impedance, gain, noise figure, input voltage standing wave ratio (VSWRin) and output signal-to-noise ratio (SNRout) without any expensive external equipment. The RF DFT scheme is based on developed theoretical expressions that produce the actual RF device specifications by output DC voltages from the DFT chip. The proposed DFT showed deviation of less than 2% as compared to expensive external equipment measurement. It is expected that this circuit can save marginally failing chips in the production testing as well as in the RF system; hence, saving tremendous amount of revenue for unnecessary device replacements.
Keywords
design-for-testability; system-on-chip; low noise amplifier; gain; noise figure; input impedance; voltage standing wave; signal-to-noise ratio;
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