• Title/Summary/Keyword: scan testing

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Low power scan testing and efficient test data compression for System-On-a-Chip

  • Jung, Jun-Mo;Chong, Jong-Wha
    • Proceedings of the IEEK Conference
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    • 2002.07a
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    • pp.228-230
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    • 2002
  • We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

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Selective Segment Bypass Scan Architecture for Test Time and Test Power Reduction (테스트 시간과 테스트 전력 감소를 위한 선택적 세그먼트 바이패스 스캔 구조)

  • Yang, Myung-Hoon;Kim, Yong-Joon;Park, Jae-Seok;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.5
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    • pp.1-8
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    • 2009
  • Since scan based testing is very efficient and widely used for testing large sequential circuits. However, since test patterns are serially injected through long scan chains, scan based testing requires very long test application time. Also, compared to the normal operations, scan shifting operations drastically increase power consumption. In order to solve these problems, this paper presents a new scan architecture for both test application time and test power reduction. The proposed scan architecture partitions scan chains into several segments and bypasses some segments which do not include any specified bit. Since bypassed segments are excluded from the scan shifting operation, the test application time and test power can be significantly reduced.

Reduction of Test Data and Power in Scan Testing for Digital Circuits using the Code-based Technique (코드 기반 기법을 이용한 디지털 회로의 스캔 테스트 데이터와 전력단축)

  • Hur, Yong-Min;Shin, Jae-Heung
    • 전자공학회논문지 IE
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    • v.45 no.3
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    • pp.5-12
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    • 2008
  • We propose efficient scan testing method capable of reducing the test data and power dissipation for digital logic circuits. The proposed testing method is based on a hybrid run-length encoding which reduces test data storage on the tester. We also introduce modified Bus-invert coding method and scan cell design in scan cell reordering, thus providing increased power saving in scan in operation. Experimental results for ISCAS'89 benchmark circuits show that average power of 96.7% and peak power of 84% are reduced on the average without fault coverage degrading. We have obtained a high reduction of 78.2% on the test data compared the existing compression methods.

Low Power Test for SoC(System-On-Chip)

  • Jung, Jun-Mo
    • Journal of information and communication convergence engineering
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    • v.9 no.6
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    • pp.729-732
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    • 2011
  • Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

An Extended Scan Path Architecture Based on IEEE 1149.1 (IEEE 1149.1을 이용한 확장된 스캔 경로 구조)

  • Son, U-Jeong;Yun, Tae-Jin;An, Gwang-Seon
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.7
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    • pp.1924-1937
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    • 1996
  • In this paper, we propose a ESP(Extended Scan Path) architecture for multi- board testing. The conventional architectures for board testing are single scan path and multi-scan path. In the single scan path architecture, the scan path for test data is just one chain. If the scan path is faulty due to short or open, the test data is not valid. In the multi-scan path architecture, there are additional signals in multi-board testing. So conventional architectures are not adopted to multi-board testing. In the case of the ESP architecture, even though scan paths either short or open, it doesn't affect remaining other scan paths. As a result of executing parallel BIST and IEEE 1149.1 boundary scan test by using, he proposed ESP architecture, we observed to the test time is short compared with the single scan path architecture. Because the ESP architecture uses the common bus, there are not additional signals in multi-board testing. By comparing the ESP architecture with conventional one using ISCAS '85 bench mark circuit, we showed that the architecture has improved results.

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A Novel High Performance Scan Architecture with Dmuxed Scan Flip-Flop (DSF) for Low Shift Power Scan Testing

  • Kim, Jung-Tae;Kim, In-Soo;Lee, Keon-Ho;Kim, Yong-Hyun;Baek, Chul-Ki;Lee, Kyu-Taek;Min, Hyoung-Bok
    • Journal of Electrical Engineering and Technology
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    • v.4 no.4
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    • pp.559-565
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    • 2009
  • Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

Efficient Parallel Scan Test Technique for Cores on AMBA-based SoC

  • Song, Jaehoon;Jung, Jihun;Kim, Dooyoung;Park, Sungju
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.3
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    • pp.345-355
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    • 2014
  • Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

Low Power Scan Testing and Test Data Compression for System-On-a-Chip (System-On-a-Chip(SOC)에 대한 효율적인 테스트 데이터 압축 및 저전력 스캔 테스트)

  • 정준모;정정화
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.12
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    • pp.1045-1054
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    • 2002
  • We present a new low power scan testing and test data compression mothod lot System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low Power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full - scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

Path Delay Testing for Micropipeline Circuits (마이크로파이프라인 회로를 위한 지연 고장 테스트)

  • Kang, Yong-Seok;Huh, Kyung-Hoi;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.8
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    • pp.72-84
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    • 2001
  • The timings of all computational elements in the micropipeline circuits are important. The previous researches on path delay testing using scan methods make little account of the characteristic of the path delay tests that the second test pattern must be more controllable. In this paper, a new scan latch is proposed which is suitable to path delay testing of the micropipelines and has small area overhead. Results show that path delay faults in the micropipeline circuits using the new scan are testable robustly and the fault coverage is higher than the previous researches. In addition, the new scan latch for path delay faults testing in the micropipeline circuits can be easily expanded to the applications such as BIST for stuck-at faults.

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Evaluation of Mechanical Properties of Structural Ceramics ($Al_{2}O_{3}$) Using the High Frequency Ultrasonic C - Scan (초음파 C-Scan을 이용한 구조용 세라믹스의 기계적 특성평가)

  • Chang, Y.K.
    • Journal of the Korean Society for Nondestructive Testing
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    • v.9 no.2
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    • pp.18-24
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    • 1989
  • Computer-aided high frequency ultrasonic is applied to aluminum oxide(85w%, 94w%, 96w%, and 99w%) MOR(modulus of rupture) samples to evaluate mechanical properties such as density variation, pore content, elastic modulus, shear modulus, and poisson's ratio. Ultrasonic wave velocity and attenuation measurement techniques were used as an evaluator of such properties. Pulse-echo C-Scan images with different fate setting method using 50MHz center frequency 1 inch focal length transducer allows evaluation of density variation and pore content. Elastic modulus calculated with the relation of density and ultrasonic velocity. It shows good reliability as compared with resonance method. Sintered density variation of $0.025g/cm^{3}$, that is 0.6% of theoretical density in $Al_{2}O_{3}$ samples can be observed by ultrasonic velocity measurement. Attenuation measurement method qualitatively agree with 4-point fracture testing result concerning of porosity content.

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