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Selective Segment Bypass Scan Architecture for Test Time and Test Power Reduction  

Yang, Myung-Hoon (Department of Electrical and Electronic Engineering, Yonsei University)
Kim, Yong-Joon (Department of Electrical and Electronic Engineering, Yonsei University)
Park, Jae-Seok (Department of Electrical and Electronic Engineering, Yonsei University)
Kang, Sung-Ho (Department of Electrical and Electronic Engineering, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.5, 2009 , pp. 1-8 More about this Journal
Abstract
Since scan based testing is very efficient and widely used for testing large sequential circuits. However, since test patterns are serially injected through long scan chains, scan based testing requires very long test application time. Also, compared to the normal operations, scan shifting operations drastically increase power consumption. In order to solve these problems, this paper presents a new scan architecture for both test application time and test power reduction. The proposed scan architecture partitions scan chains into several segments and bypasses some segments which do not include any specified bit. Since bypassed segments are excluded from the scan shifting operation, the test application time and test power can be significantly reduced.
Keywords
Scan based testing; scan architecture; test application time; test power; segment bypass;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
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