Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Low Power Scan Testing and Test Data Compression for System-On-a-Chip

System-On-a-Chip(SOC)에 대한 효율적인 테스트 데이터 압축 및 저전력 스캔 테스트

  • 정준모 (김포대학 전자정보계열) ;
  • 정정화 (한양대학교 정보통신대학 정보통신학부)
  • Published : 2002.12.01
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Abstract

We present a new low power scan testing and test data compression mothod lot System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low Power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full - scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

System-On-a-Chip(SOC)에 대하여 테스트 데이터 압축 및 저전력 스캔테스팅에 대한 새로운 알고리즘을 제안하였다. 스캔벡터내의 don't care 입력들을 저전력이 되도록 적절하게 값을 할당하였고 높은 압축율을 갖도록 적응적 인코딩을 적용하였다. 또한 스캔체인에 입력되는 동안 소모되는 scan-in 전력소모를 최소화하도록 스캔벡터의 입력 방향을 결정하였다. ISCAS 89 벤치마크 회로에 대하여 실험한 결과는 평균전력 소모는 약 12% 감소되었고 압축율은 약 60%가 향상됨을 보였다.

Keywords

References

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