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http://dx.doi.org/10.5573/JSTS.2014.14.3.345

Efficient Parallel Scan Test Technique for Cores on AMBA-based SoC  

Song, Jaehoon (Dept. of Computer Science & Engineering, Hanyang University ERICA Campus)
Jung, Jihun (Dept. of Computer Science & Engineering, Hanyang University ERICA Campus)
Kim, Dooyoung (Dept. of Computer Science & Engineering, Hanyang University ERICA Campus)
Park, Sungju (Dept. of Computer Science & Engineering, Hanyang University ERICA Campus)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.14, no.3, 2014 , pp. 345-355 More about this Journal
Abstract
Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.
Keywords
AMBA; system-on-a-chip; scan test; IEEE 1500; parallel test; test time;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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