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Low Power Scan Testing and Test Data Compression for System-On-a-Chip  

정준모 (김포대학 전자정보계열)
정정화 (한양대학교 정보통신대학 정보통신학부)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.12, 2002 , pp. 1045-1054 More about this Journal
Abstract
We present a new low power scan testing and test data compression mothod lot System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low Power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full - scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.
Keywords
테스트 데이터 압축;저전력;스캔테스트;
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