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http://dx.doi.org/10.6109/ijice.2011.9.6.729

Low Power Test for SoC(System-On-Chip)  

Jung, Jun-Mo (Department of Electronics Engineering, Kunsan National University)
Publication Information
Journal of information and communication convergence engineering / v.9, no.6, 2011 , pp. 729-732 More about this Journal
Abstract
Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.
Keywords
SoC; low power test; scan circuit;
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