• Proceedings of the Materials Research Society of Korea Conference
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• 1993.05a
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• pp.43-44
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• 1993

In this study SOI MOSFET model of the structure with 4-terminals and 3-interfaces is proposed. An SOI MOSFET is modeled with the equivalent circuit considered the interface capacitances. Parameters of SOI MOSFET device are extracted, and the electrical characteristics due to back-bias change is simulated. In SOI-MOSFET model device we describe the characteristics of threshold voltage, subthreshold slope, maxium electrical field and drain currents in the front channel when the back channel condition move into accmulation, depletion, and inversion regions respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2045-2051
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• 2009

A 5-GHz band Low Noise Amplifier(LNA) using SOI MOSFET is designed. To improve the noise performance, depletion-type SOI MOSFET is adopted, and it is designed by the two-stage topology consisting of common-source and common-gate stages for low-voltage operation. The fabricated LNA achieved an S11 of less than -10dB, voltage gain of 21dB with a power consumption of 8.3mW at 5.5GHz, and a noise figure of 1.7dB indicated that the depletion-type LNA improved the noise figure by 0.3dB compared with conventional type. These results show the feasibility of a CMOS LNA employing depletion-type SOI MOSFET for low-noise application.

• Proceedings of the Materials Research Society of Korea Conference
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• 2005.05a
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• pp.53-53
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• 2005

• ETRI Journal
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• v.26 no.6
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• pp.575-582
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• 2004

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.11
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• pp.939-942
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• 2007

We investigated the characteristics of UTB-SOI pMOSFETs with SOI thickness($T_{SOI}$) ranging from 10 nm to 1 nm and evaluated the dependence of electrical characteristics on the silicon surface orientation. As a result, it is found that the subthreshold characteristics of (100)-surface UTB-SOI pMOSFETs were superior to (110)-surface. However, the hole mobility of (110)-surface were larger than that of (100)-surface. Especially, the enhancement of effective hole mobility at the effective field of 0.1 MV/cm was observed from 3-nm to 5-nm SOI thickness range.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.285-285
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• 2011

최근 반도체 소자의 미세화에 따라, 단채널 효과에 의한 누설전류 및 소비전력의 증가 등이 문제되고 있다. 대표적인 휘발성 메모리인 dynammic random access memory (DRAM)의 경우, 소자의 집적화가 진행됨에 따라 저장되는 정보의 양을 유지하기 위해 캐패시터영역의 복잡한 공정을 요구하게 된다. 하나의 캐패시터와 하나의 트랜지스터로 이루어진 기존의 DRAM과 달리, single transistor (1T) DRAM은 silicon-on-insulator (SOI) 기술을 기반으로 하여, 하나의 트랜지스터로 DRAM 동작을 구현한다. 이러한 구조적인 이점 이외에도, 우수한 전기적 절연 특성과 기생 정전용량 및 소비 전력의 감소 등의 장점을 가지고 있다. 또한 strained-Si 층을 적용한 strained-Silicon-On-Insulator (sSOI) 기술을 이용하여, 전기적 특성 및 메모리 특성의 향상을 기대 할 수 있다. 본 연구에서는 sSOI 기판위에 1T-DRAM을 구현하였으며, impact ionization과 gate induced-drain-leakage (GIDL) 전류에 의한 메모리 구동 방법을 통해 sSOI 1T-DRAM의 메모리 특성을 평가하였다. 그 결과 strain 효과에 의한 전기적 특성의 향상을 확인하였으며, GIDL 전류를 이용한 메모리 구동 방법을 사용했을 경우 낮은 소비 전력과 개선된 메모리 윈도우를 확인하였다.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.553-556
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• 1998

The 1-D numerical model and its extraction methodology are suggested and these simulation results for the S-swing as a function of back-gate voltage are well matched with the measured. S-swing characteristics are analyzed using PD-SOI devices with enough deeper regions up to substrates. The PD-SOI device doesn't have to be short channel to see the anomalous subthreshold phenomena based on the back gate bias. This results recommend to operate better SOI device performances by controlling the back gate voltages. So SOI performances will be much optimistic with proper control of the back-gate voltage for the already- proven- high- performance (APHP) SOI VLSIs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.485-488
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• 1999

In this paper, the effects of back-gate bias on n-channel SOI MOSFETs has been systematically investigated. Back-gate surface is accumulated when negative bias is applied. It is found that the driving current ability of SOI MOSFETs is reduced because the threshold voltage and subthreshold slope are increased and transconductance is decreased due to the hole accumulation in Si body.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.6
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• pp.428-435
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• 1998

SOI-like-bulk CMOS device is proposed, which having the advantages of SOI(Silicon On Insulator) and protects short channel effects efficiently with adding partial epitaxial process at standard CMOS process. SOI-like-bulk NMOS and PMOS with 0.25${\mu}{\textrm}{m}$ gate length have designed and optimized through analyzing the characteristics of these devices and applying again to the design of processes. The threshold voltages of the designed NMOS and PMOS are 0.3[V], -0.35[V] respectively and those have shown the stable characteristics under 1.5[V] gate and drain voltages. The leakage current of typical bulk-CMOS increase with shortening the channel length, but the proposed structures on this a study reduce the leakage current and improve the subthreshold characteristics at the same time. In addition, subthreshold swing value, S is 70.91[mV/decade] in SOI-like-bulk NMOS and 63.37[mV/ decade] SOI-like-bulk PMOS. And the characteristics of SOI-like-bulk CMOS are better than those of standard bulk CMOS. To validate the circuit application, CMOS inverter circuit has designed and transient & DC transfer characteristics are analyzed with mixed mode simulation.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.5
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• pp.959-964
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• 2018

In this paper, it was firstly confirmed that the drain current of the depleted SOI MOSFET operated in the high frequency response delay occurs by the inductive parasitic. Depleted SOI MOSFET cannot be applied as a conventional high-frequency MOSFET model because the response delay of the drain current is generated in accordance with the drain voltage fluctuation. This response delay may be described as a non-quasi-static effect, and the SOI MOSFET generated the response delay by the inductive parasitics compared to typical MOSFET. It is confirmed that depleted SOI MOSFET's RF characteristics can be well reproduced with the proposed method including the drain current response delay.