• ETRI Journal
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• v.44 no.3
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• pp.491-503
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• 2022

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

• Journal of Powder Materials
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• v.27 no.3
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• pp.203-209
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• 2020

The automotive industry has focused on the development of metallic materials with high specific strength, which can meet both fuel economy and safety goals. Here, a new class of ultrafine-grained high-Mn steels containing nano-scale oxides is developed using powder metallurgy. First, high-energy mechanical milling is performed to dissolve alloying elements in Fe and reduce the grain size to the nanometer regime. Second, the ball-milled powder is consolidated using spark plasma sintering. During spark plasma sintering, nanoscale manganese oxides are generated in Fe-15Mn steels, while other nanoscale oxides (e.g., aluminum, silicon, titanium) are produced in Fe-15Mn-3Al-3Si and Fe-15Mn-3Ti steels. Finally, the phases and resulting hardness of a variety of high-Mn steels are compared. As a result, the sintered pallets exhibit superior hardness when elements with higher oxygen affinity are added; these elements attract oxygen from Mn and form nanoscale oxides that can greatly improve the strength of high-Mn steels.

• Journal of the Korean Society for Nondestructive Testing
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• v.32 no.2
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• pp.115-121
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• 2012

Exploration in microelectromechanical systems(MEMS) and nanotechnology requires evaluation techniques suitable for sub-micron length scale so that thermal and mechanical properties of novel materials can be investigated for optimal design of miro/nanostructures. The ultrafast optical pump-probe technique provides a contact-free and non-destructive way to characterize nanoscale thin-films, and its ultrahigh temporal resolution enables the study of heat-transport phenomena down to a sub-picosecond regime. This paper reviews the principle of optical pump-probe technique and introduces its application to the area of micro/nano-NDE.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.66-74
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• 2012

In this paper, the impact of segregation layer density ($N_{DSL}$) and length ($L_{DSL}$) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the $N_{DSL}$ the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the $L_{DSL}$ the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a common-source amplifier based on optimized DSSB SOI MOSFET has improved by ~40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing $N_{DSL}$ and $L_{DSL}$ of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits.

• Transactions on Electrical and Electronic Materials
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• v.11 no.3
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• pp.93-105
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• 2010

Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past three decades. However, as the technology scaling enters nanometer regime, CMOS devices are facing many serious problems such as increased leakage currents, difficulty on increase of on-current, large parameter variations, low reliability and yield, increase in manufacturing cost, and etc. To sustain the historical improvements, various innovations in CMOS materials and device structures have been researched and introduced. In parallel with those researches, various new nanoelectronic devices, so called "Beyond CMOS Devices," are actively being investigated and researched to supplement or possibly replace ultimately scaled conventional CMOS devices. While those nanoelectronic devices offer ultra-high density system integration, they are still in a premature stage having many critical issues such as high variations and deteriorated reliability. The practical realization of those promising technologies requires extensive researches from device to system architecture level. In this paper, the current researches and challenges on nanoelectronics are reviewed and critical tasks are summarized from device level to circuit design/CAD domain to better prepare for the forthcoming technologies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.585-593
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• 2015

In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.102-102
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• 2016

Water, which is most abundant in Earth surface and very closely related to all forms of living organisms, has a simple molecular structure but exhibits very unique physical and chemical properties. Even though tremendous effort has been paid to understand this nature's core substance, there amazingly still lefts much room for scientist to explore its novel behaviors. Especially, as the scale goes down to nano-regime, water shows extraordinary properties that are not observable in bulk state. One of such interesting features is the formation of nanoscale bubbles showing unusual long-term stability. Nanobubbles can be spontaneously formed in water on hydrophobic surface or by decompression of gas-saturated liquid. In addition, the nanobubbles can be generated during electrochemical reaction at normal hydrogen electrode (NHE), which possibly distorts the standard reduction potential at NHE as the surface nanobubble screens the reaction with electrolyte solution. However, the real-time evolution of these nanobubbles has been hardly studied owing to the lack of proper imaging tools in liquid phase at nanoscale. Here we demonstrate, for the first time, that the behaviors of nanobubbles can be visualized by in situ transmission electron microscope (TEM), utilizing graphene as liquid cell membrane. The results indicate that there is a critical radius that determines the long-term stability of nanobubbles. In addition, we find two different pathways of nanobubble growth: i) Ostwald ripening of large and small nanobubbles and ii) coalescence of similar-sized nanobubbles. We also observe that the nucleation and growth of nanoparticles and the self-assembly of biomolecules are catalyzed at the nanobubble interface. Our finding is expected to provide a deeper insight to understand unusual chemical, biological and environmental phenomena where nanoscale gas-state is involved.

• Advances in nano research
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• v.15 no.6
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• pp.521-531
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• 2023

Quantum-dot cellular automata (QCA) has shown great potential in the nanoscale regime as a replacement for CMOS technology. This work presents a specific approach to static random-access memory (SRAM) cell based on 2:1 multiplexer, 4-bit SRAM array, and 32-bit SRAM array in QCA. By utilizing the proposed SRAM array, a single-layer 16×32-bit SRAM with the read/write capability is presented using an optimized signal distribution network (SDN) crossover technique. In the present study, an extremely-optimized 2:1 multiplexer is proposed, which is used to implement an extremely-optimized SRAM cell. The results of simulation show the superiority of the proposed 2:1 multiplexer and SRAM cell. This study also provides a more efficient and accurate method for calculating QCA costs. The proposed extremely-optimized SRAM cell and SRAM arrays are advantageous in terms of complexity, delay, area, and QCA cost parameters in comparison with previous designs in QCA, CMOS, and FinFET technologies. Moreover, compared to previous designs in QCA and FinFET technologies, the proposed structure saves total energy consisting of overall energy consumption, switching energy dissipation, and leakage energy dissipation. The energy and structural analyses of the proposed scheme are performed in QCAPro and QCADesigner 2.0.3 tools. According to the simulation results and comparison with previous high-quality studies based on QCA and FinFET design approaches, the proposed SRAM reduces the overall energy consumption by 25%, occupies 33% smaller area, and requires 15% fewer cells. Moreover, the QCA cost is reduced by 35% compared to outstanding designs in the literature.

• Korean Journal of Crystallography
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• v.16 no.2
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• pp.89-101
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• 2005

Among many material processing related issues for successful scaling down of devices for the next 10 years or so, the advanced gate stack and interconnect technology are two most critical research areas, which need technical innovation. The introduction of new metallic films and appropriate processing technologies are required more than ever. Especially, as the device downscaling continues well into sub 50 nm regime, the paradigm for metal nano film deposition technique research has been shifted to high conformality, low growth temperature, high quality with uniformity at large area wafers. Regarding these, ALD has sparked a lot of interests for a number of reasons. The process is intrinsically atomic in nature, resulting in the controlled deposition of films in sub-monolayer units with excellent conformality. In this paper, the overview on the current issues and the future trends in device processing technologies related to metal nano films as well as the R&D trends in these applications will be discussed. The focus will be on the applications for metal gate, capacitor electrode for DRAM, and diffusion barriers/seed layers for Cu interconnect technology.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.2
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• pp.70-77
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• 2007

The application of focused ion beam(FIB) technology has been broadened in the fabrication of nanoscale regime. The extended application of FIB is dependent on complicated reciprocal relation of operating parameters. It is necessary for successful and efficient modifications on the surface of silicon substrate. The primary effect by Gaussian beam intensity is significantly shown from various aperture size, accelerating voltage, and beam current. Also, the secondary effect of other process factors - dwell time, pixel interval, scan mode, and pattern size has affected to etching results. For the process analysis, influence of the secondary factors on FIB micromilling process is examined with respect to sputtering depth during the milling process in silicon material. The results are analyzed by the ratio of signal to noise obtained using design of experiment in each parameter.