Transactions on Electrical and Electronic Materials

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
권호 표지
DOI QR코드

DOI QR Code

Challenges for Nanoscale MOSFETs and Emerging Nanoelectronics

  • Kim, Yong-Bin (Department of Electrical and Computer Engineering, Northeastern University)
  • Received : 2010.04.26
  • Accepted : 2010.05.03
  • Published : 2010.06.25
Download PDF
⟨ Previous Next ⟩

Abstract

Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past three decades. However, as the technology scaling enters nanometer regime, CMOS devices are facing many serious problems such as increased leakage currents, difficulty on increase of on-current, large parameter variations, low reliability and yield, increase in manufacturing cost, and etc. To sustain the historical improvements, various innovations in CMOS materials and device structures have been researched and introduced. In parallel with those researches, various new nanoelectronic devices, so called "Beyond CMOS Devices," are actively being investigated and researched to supplement or possibly replace ultimately scaled conventional CMOS devices. While those nanoelectronic devices offer ultra-high density system integration, they are still in a premature stage having many critical issues such as high variations and deteriorated reliability. The practical realization of those promising technologies requires extensive researches from device to system architecture level. In this paper, the current researches and challenges on nanoelectronics are reviewed and critical tasks are summarized from device level to circuit design/CAD domain to better prepare for the forthcoming technologies.

Keywords

References

  1. H. Iwai, Extended Abstracts 2008 8th International Workshop on Junction Technology (IWJT '08) (Shanghai, China 2008 May 15-16, IEEE Press) p. 1. [DOI: 10.1109/IWJT.2008.4540004].
  2. G. E. Moore, Electronics 38, (1965).
  3. G. E. Moore, International Electron Devices Meeting. Technical Digest (Washington, DC 1975 Dec. 1-3, IEEE Group on Electron Devices) p. 11.
  4. International Technology Roadmap for Semiconductors(ITRS) 2007 Edition. Available from: http://www.itrs.net/links/2007ITRS/Home2007.htm.
  5. D. Kahng and M. M. Atalla, the IRE Solid-State Device Research Conference (Pittsburgh, PA 1960 Jun., Carnegie Institute of Technology).
  6. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, IEEE J. Solid-State Circuits SC-9, 256 (1974).
  7. D. A. Antoniadis, I. Aberg, C. Ní Chleirigh, O. M. Nayfeh, A. Khakifirooz, and J. L. Hoyt, IBM J. Res. Dev. 50, 363 (2006) [DOI: 10.1147/rd.504.0363].
  8. M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, and K. Bernstein, IEEE International Electron Devices Meeting. IEDM Technical Digest (Washington, DC 2005 Dec. 5-7, IEEE Group on Electron Devices) p. 7. [DOI: 10.1109/IEDM.2005.1609253].
  9. H. S. P. Wong, D. J. Frank, P. M. Solomon, C. H. J. Wann, and J. J. Welser, Proc. IEEE 87, 537 (1999) [DOI: 10.1109/5.752515].
  10. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H. S. P. Wong, Proc. IEEE 89, 259 (2001) [DOI: 10.1109/5.915374].
  11. B. Razavi, Design of Analog CMOS Integrated Circuits (McGraw-Hill, Boston, MA, 2001).
  12. M. Stockinger, Optimization of Ultra-Low-Power CMOS Transistors, Ph.D. dissertation (Vienna, Austria 2000, Institute for Microelectronics).
  13. R. R. Troutman, IEEE J. Solid-State Circuits 14, 383 (1979). https://doi.org/10.1109/JSSC.1979.1051189
  14. I. M. Bateman, G. A. Armstrong, and J. A. Magowan, 19th International Electron Devices Meeting. Technical Digest (Washington, DC 1973 Dec. 3-5, IEEE Group on Electron Devices) p. 147.
  15. S. Ogura, P. J. Tsang, W. W. Walker, D. L. Critchlow, and J. F. Shepard, IEEE J. Solid-State Circuits 15, 424 (1980). https://doi.org/10.1109/JSSC.1980.1051416
  16. S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era, Vol. 3: The Submicron MOSFET (Lattice Press, Sunset Beach, CA, 1986).
  17. I. De and C. M. Osburn, IEEE Trans Electron Devices 46, 1711 (1999) [DOI: 10.1109/16.777161].
  18. T. Mizuno, J.-I. Okamura, and A. Toriumi, IEEE Trans. Electron Devices 41, 2216 (1994) [DOI: 10.1109/16.333844].
  19. A. Asenov, G. Slavcheva, A. R. Brown, J. H. Davies, and S. Saini, IEEE Trans. Electron Devices 48, 722 (2001) [DOI: 10.1109/16.915703].
  20. Y. Ye, F. Liu, S. Nassif, and Y. Cao, Proceedings of the 45th Annual Design Automation Conference (Anaheim, CA 2008 Jun. 8-13, ACM/IEEE) p. 900. [DOI: 10.1145/1391469.1391698].
  21. R. F. Pierret, Semiconductor Device Fundamentals (Addison-Wesley, Reading, MA, 1996) p. 691.
  22. B. L. Anderson and R. L. Anderson, Fundamentals of Semiconductor Devices (McGraw-Hill Higher Education, Boston, 2005) p. 124, p. 425.
  23. P. A. Gargini, International Symposium on VLSI Technology Systems and Applications (VLSI-TSA) (Hsinchu 2008 Apr. 21-23, IEEE) p. 10. [DOI: 10.1109/VTSA.2008.4530775].
  24. V. V. Zhirnov, R. K. Cavin Iii, J. A. Hutchby, and G. I. Bourianoff, Proc. IEEE 91, 1934 (2003) [DOI: 10.1109/JPROC.2003.818324].
  25. V. George, S. Jahagirdar, C. Tong, K. Smits, S. Damaraju, S. Siers, V. Naydenov, T. Khondker, S. Sarkar, and P. Singh, 2007 IEEE Asian Solid-State Circuits Conference (A-SSCC) ( Jeju, Korea 2007 Nov. 12-14, IEEE) p. 14. [DOI: 10.1109/ASSCC.2007.4425784].
  26. P. J. Wright and K. C. Saraswat, IEEE Trans. Electron Devices 37, 1884 (1990) [DOI: 10.1109/16.57140].
  27. G. D. Wilk, R. M. Wallace, and J. M. Anthony, J. Appl. Phys. 89, 5243 (2001) [DOI: 10.1063/1.1361065].
  28. G. M. T. Wong, An Investigation of the Work Function of Metal Gate Electrodes for Advanced CMOS Applications, Ph.D. dissertation (Palo Alto, CA 2008, Stanford University).
  29. K. S. Chang, M. L. Green, J. R. Hattrick-Simpers, I. Takeuchi, J. S. Suehle, O. Celik, and S. De Gendt, IEEE Trans. Electron Devices 55, 2641 (2008) [DOI: 10.1109/TED.2008.2003091].
  30. S. D. Kim, C. M. Park, and J. C. S. Woo, IEEE Trans. Electron Devices 49, 457 (2002) [DOI: 10.1109/16.987117].
  31. T. Krishnamohan, Physics and Technology of High Mobility, Strained Germanium Channel, Heterostructure MOSFETs, Ph.D. dissertation (Palo Alto, CA 2006, Stanford University).
  32. M. Ieong, IEEE Nanotechnology Materials and Devices Conference (NMDC) (Gyeongju, Korea 2006 Oct. 22-25, IEEE) p. 88. [DOI: 10.1109/NMDC.2006.4388702].
  33. M. C. Chang, C. S. Chang, C. P. Chao, K. I. Goto, M. Ieong, L. C. Lu, and C. H. Diaz, IEEE Trans. Electron Devices 55, 84 (2008) [DOI: 10.1109/TED.2007.911348].
  34. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, Proc. IEEE 91, 305 (2003) [DOI: 10.1109/JPROC.2002.808156].
  35. K. C. Saraswat, International Symposium on VLSI Technology Systems and Applications (VLSI-TSA) (Hsinchu 2007 Apr. 23-25, IEEE) p. 1. [DOI: 10.1109/VTSA.2007.378944].
  36. S. A. Parke, J. E. Moon, H.-j. C. Wann, P. K. Ko, and C. Hu, IEEE Trans. Electron Devices 39, 1694 (1992) [DOI: 10.1109/16.141236].
  37. Y. Xiaobin, P. Jae-Eun, W. Jing, Z. Enhai, D. Ahlgren, T. Hook, Y. Jun, V. Chan, S. Huiling, L. Chu-Hsin, R. Lindsay, P. Sungjoon, and C. Hyotae, IEEE International Integrated Reliability Workshop Final Report (IRW 2007) (South Lake Tahoe, CA 2007 Oct. 15-18, IEEE) p. 70. [DOI: 10.1109/IRWS.2007.4469224].
  38. L. Chang, Y. K. Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, C. Hu, and T. J. King, Proc. IEEE 91, 1860 (2003) [DOI: 10.1109/JPROC.2003.818336].
  39. T. Sakurai, A. Matsuzawa, and T. Douseki, Fully-Depleted SOI CMOS Circuits and Technology for Ultra-Low Power Applications (Springer, Dordrecht, The Netherlands, 2006).
  40. R. Simonton, Special Report SOI Wafer Technology for CMOS ICs [Electronic Document] (Simonton Associates, 2002) Available from: http://www.icknowledge.com/threshold_simonton/soitechnology.pdf.
  41. A. Jakubowski and L. LUkasiak, Mater. Sci. -Poland 26, 5 (2008).
  42. D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. J. King, F. Jeffrey Bokor, and C. Hu, IEEE Trans. Electron Devices 47, 2320 (2000). https://doi.org/10.1109/16.887014
  43. A. K. Sharma and A. Teverovsky, Reliability Evaluation of Fully Depleted SOI (FDSOI) Technology for Space Applications [Electronic Document] (NASA Electronic Parts and Packaging (NEPP) Program, 2001). Available from: http://nepp.nasa.gov/docuploads/f8b88988-9a2d-462b-986eb801f50978a9/eval_fdsoiparti_neppfinalreport.pdf.
  44. N. Mohta and S. E. Thompson, IEEE Circuits Devices Mag. 21, 18 (2005) [DOI: 10.1109/MCD.2005.1517386].
  45. W. Chee, S. Maikop, and C. Y. Yu, IEEE Circuits Devices Mag. 21, 21 (2005) [DOI: 10.1109/MCD.2005.1438752].
  46. C. K. Maiti, International Workshop on Physics of Semiconductor Devices (IWPSD 2007) (Mumbai, India 2007 Dec. 16-20, IEEE) p. 52. [DOI: 10.1109/IWPSD.2007.4472453].
  47. C. Auth, M. Buehler, A. Cappellani, C.-h. Choi, G. Ding, W. Han, S. Joshi, B. McIntyre, M. Prince, P. Ranade, J. Sandford, and C. Thomas, Intel Tech. J. 12, 77 (2008) [DOI: 10.1535/itj.1202.01].
  48. C. M. Lieber and Z. L. Wang, MRS Bull. 32, 99 (2007). https://doi.org/10.1557/mrs2007.41
  49. W. Lu and C. M. Lieber, J. Phys. D: Appl. Phys. 39, R387 (2006) [DOI: 10.1088/0022-3727/39/21/R01].
  50. A. M. Morales and C. M. Lieber, Science 279, 208 (1998) [DOI: 10.1126/science.279.5348.208].
  51. W. Lu, J. Xiang, B. P. Timko, Y. Wu, and C. M. Lieber, Proc. Natl. Acad. Sci. U.S.A. 102, 10046 (2005) [DOI: 10.1073/pnas.0504581102].
  52. J. Xiang, W. Lu, Y. Hu, Y. Wu, H. Yan, and C. M. Lieber, Nature 441, 489 (2006) [DOI: 10.1038/nature04796].
  53. Y. Wu, Y. Cui, L. Huynh, C. J. Barrelet, D. C. Bell, and C. M. Lieber, Nano Lett. 4, 433 (2004) [DOI: 10.1021/nl035162i].
  54. W. Lu, P. Xie, and C. M. Lieber, IEEE Trans. Electron Devices 55, 2859 (2008) [DOI: 10.1109/TED.2008.2005158].
  55. M. J. Kumar, M. A. Reed, G. A. J. Amaratunga, G. M. Cohen, D. B. Janes, C. M. Lieber, M. Meyyappan, L. E. Wernersson, K. L. Wang, R. S. Chau, T. I. Kamins, M. Lundstrom, B. Yu, and C. Zhou, IEEE Trans. Electron Devices 55, 2813 (2008) [DOI: 10.1109/TED.2008.2006781].
  56. S. Iijima, Nature 354, 56 (1991) [DOI: 10.1038/354056a0].
  57. H. Dai, Surf. Sci. 500, 218 (2002) [DOI: 10.1016/S0039-6028(01)01558-8].
  58. M. S. Dresselhaus, G. Dresselhaus, and P. Avouris, Carbon nanotubes: Synthesis, Structure, Properties, and Applications (Springer, Berlin; New York, 2001).
  59. P. Avouris, J. Appenzeller, R. Martel, and S. J. Wind, Proc. IEEE 91, 1772 (2003) [DOI: 10.1109/JPROC.2003.818338].
  60. N. Srivastava and K. Banerjee, IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2005) (San Jose, CA 2005, IEEE/ACM) p. 383. [DOI: 10.1109/ICCAD.2005.1560098].
  61. V. V. Zhirnov, J. A. Hutchby, G. I. Bourianoff, and J. E. Brewer, IEEE Circuits Devices Mag. 21, 37 (2005) [DOI: 10.1109/MCD.2005.1438811].
  62. M. Lundstrom, Proceedings of the 2002 International Symposium on Low Power Electronics and Design (ISLPED '02) (Monterey, CA 2002, IEEE) p. 172.
  63. J. Appenzeller, Proc. IEEE 96, 201 (2008) [DOI: 10.1109/JPROC.2007.911051].
  64. K. S. Novoselov, A. K. Geim, S. V. Morozov, D. Jiang, Y. Zhang, S. V. Dubonos, I. V. Grigorieva, and A. A. Firsov, Science 306, 666 (2004) [DOI: 10.1126/science.1102896].
  65. W. A. De Heer, C. Berger, E. Conrad, P. First, R. Murali, and J. Meindl, IEEE International Electron Devices Meeting (IEDM) (Washington, DC 2007 Dec. 10-12, IEEE) p. 199. [DOI: 10.1109/IEDM.2007.4418901].
  66. M. Y. Han, B. Ozyilmaz, Y. Zhang, and P. Kim, Phys. Rev. Lett. 98(2007) [DOI: 10.1103/PhysRevLett.98.206805].
  67. X. Li, X. Wang, L. Zhang, S. Lee, and H. Dai, Science 319, 1229 (2008) [DOI: 10.1126/science.1150878].
  68. Y. W. Son, M. L. Cohen, and S. G. Louie, Phys. Rev. Lett. 97(2006) [DOI: 10.1103/PhysRevLett.97.216803].
  69. K. Mohanram and J. Guo, International Conference on Computer-Aided Design (ICCAD) (San Jose, CA 2008, IEEE) p. 412. [DOI: 10.1109/ICCAD.2008.4681607].
  70. M. Choudhury, Y. Yoon, J. Guo, and K. Mohanram, 45th Design Automation Conference (DAC) (Anaheim, CA 2008, ACM) p. 272. [DOI: 10.1109/DAC.2008.4555822].
  71. Y. Takahashi, A. Fujiwara, Y. Ono, and K. Murase, 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL'2000) (Portland, OR 2000, IEEE) p. 411.
  72. K. K. Likharev, Proc. IEEE 87, 606 (1999) [DOI: 10.1109/5.752518].
  73. C. Wasshuber, Computational Single-Electronics (Springer, Wien; New York, 2001).
  74. H. Inokawa, A. Fujiwara, and Y. Takahashi, IEEE Trans. Electron Devices 50, 462 (2003) [DOI: 10.1109/TED.2002.808421].
  75. K. W. Song, Y. K. Lee, J. S. Sim, H. Jeoung, J. D. Lee, B. G. Park, Y. S. Jin, and Y. W. Kim, IEEE Trans. Electron Devices 52, 1845 (2005) [DOI: 10.1109/TED.2005.852730].
  76. M. Saitoh, H. Harata, and T. Hiramoto, IEEE International Electron Devices Meeting (IEDM) (San Francisco, CA 2004 Dec 13-15, IEEE) p. 187. [DOI: 10.1109/IEDM.2004.1419104].
  77. S. Bandyopadhyay and V. Roychowdhury, Jpn. J. Appl. Phys. 35, 3350 (1996) [DOI: 10.1143/JJAP.35.335].
  78. K. S. Park, S. J. Kim, I. B. Back, W. H. Lee, J. S. Kang, Y. B. Jo, S. D. Lee, C. K. Lee, J. B. Choi, J. H. Kim, K. H. Park, W. J. Cho, M. G. Jang, and S. J. Lee, IEEE Trans Nanotechnol. 4, 242 (2005) [DOI: 10.1109/TNANO.2004.837857].
  79. V. V. Zhirnov, J. A. Hutchby, G. I. Bourianoffls, and J. E. Brewer, IEEE Circuits Devices Mag. 21, 37 (2005) [DOI: 10.1109/MCD.2005.1438811].
  80. R. H. Chen, A. N. Korotkov, and K. K. Likharev, Appl. Phys. Lett. 68, 1954 (1996) [DOI: 10.1063/1.115637].
  81. K. Nishiguchi, A. Fujiwara, Y. Ono, H. Inokawa, and Y. Takahashi, Appl. Phys. Lett. 88, 183101 (2006) [DOI: 1063/1.2200475]. https://doi.org/10.1063/1.2200475
  82. K. Uchida, T. Tanamoto, R. Ohba, S. I. Yasuda, and S. Fujita, IEEE International Devices Meeting (IEDM) (San Francisco, CA 2002 Dec. 8-11, IEEE) p. 177.
  83. N. Asahi, M. Akazawa, and Y. Amemiya, IEEE Trans. Electron Devices 44, 1109 (1997) [DOI: 10.1109/16.595938].
  84. C. S. Lent and P. D. Tougaw, J. Appl. Phys. 74, 6227 (1993) [DOI: 10.1063/1.355196].
  85. P. D. Tougaw and C. S. Lent, J. Appl. Phys. 75, 1818 (1994) [DOI: 10.1063/1.356375].
  86. C. S. Lent, P. D. Tougaw, W. Porod, and G. H. Bernstein, Nanotechnology 4, 49 (1993) [DOI: 10.1088/0957-4484/4/1/004].
  87. G. L. Snider, A. O. Orlov, V. Joshi, R. A. Joyce, Q. Hua, K. K. Yadavalli, G. H. Bernstein, T. P. Fehlner, and C. S. Lent, 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT 2008) (Bajing, China 2008 Oct. 20-23) p. 549. [DOI: 10.1109/ICSICT.2008.4734600].
  88. G. L. Snider, A. O. Orlov, R. K. Kummamuru, R. Ramasubramaniam, I. Amlani, G. H. Bernstein, C. S. Lent, J. L. Merz, and P. Wolfgang, Proceedings of the 2001 1st IEEE Conference on Nanotechnology (IEEE-NANO 2001) (Maui, HI 2008 Oct. 28-30, IEEE) p. 465. [DOI: 10.1109/NANO.2001.966468].
  89. J. A. Hutchby, R. Cavin, V. Zhirnov, J. E. Brewer, and G. Bourianoff, Computer 41, 28 (2008) [DOI: 10.1109/MC.2008.154].
  90. A. K. Goel, High-Speed VLSI Interconnections, 2nd ed. (Wiley-Interscience; IEEE Press, Hoboken, NJ, 2007).
  91. A. K. Goel, IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2008) (Niagara Falls, ON 2008 May 4-7, IEEE) p. 189. [DOI: 10.1109/CCECE.2008.4564521].
  92. A. Orailoglu, 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, Workshop on Dependable and Secure Nanocomputing (Edinburgh, UK 2007 Jun. 25-28, IEEE/IFIP). Available from: http://www.laas.fr/WDSN07/WDSN07_files/Texts/WDSN07-8D-04-Orailoglu.pdf.
  93. R. I. Bahar, D. Hammerstrom, J. Harlow, W. H. Joyner Jr, C. Lau, D. Marculescu, A. Orailoglu, and M. Pedram, IEEE Computer, 40, 25 (2007)[DOI: 10.1109/MC.2007.7].
  94. A. DeHon and K. K. Likharev, IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2005) (San Jose, CA 2005 Nov. 6-10, IEEE) p. 375. [DOI: 10.1109/ICCAD.2005.1560097].
  95. G. D. Hachtel and F. Somenzi, Logic Synthesis and Verification Algorithms, 2nd print., with corrections ed. (Kluwer Academic Publishers, Boston, 1998), pp. 25-41.
  96. G. De Micheli, Synthesis and Optimization of Digital Circuits (McGraw-Hill, New York, 1994), pp. 75-97.
  97. R. Zhang, Computer-Aided Design Algorithms and Tools for Nanotechnologies, Ph.D. dissertation (Princeton, NJ 2008, Princeton University).
  98. S. C. Goldstein, Proceedings of Government Microcircuit Applications and Critical Technology Conference (GOMAC Tech 04) (Monterey, CA 2004).

Cited by

  1. OPAMP Design Using Optimized Self-Cascode Structures vol.15, pp.3, 2014, https://doi.org/10.4313/TEEM.2014.15.3.149
  2. Electrical, optical, structural and chemical properties of Al 2 TiO 5 films for high-к gate dielectric applications vol.57, 2017, https://doi.org/10.1016/j.mssp.2016.10.019
  3. Review on analog/radio frequency performance of advanced silicon MOSFETs vol.32, pp.12, 2017, https://doi.org/10.1088/1361-6641/aa9145
  4. Analytical modeling of subthreshold characteristics of ultra-thin double gate-all-around (DGAA) MOSFETs incorporating quantum confinement effects vol.109, 2017, https://doi.org/10.1016/j.spmi.2017.05.038
  5. An output node split CMOS logic for high-performance and large capacitive-load driving scenarios vol.72, 2018, https://doi.org/10.1016/j.mejo.2017.12.010
  6. Performance Evaluation of Efficient XOR Structures in Quantum-Dot Cellular Automata (QCA) vol.04, pp.02, 2013, https://doi.org/10.4236/cs.2013.42020
  7. Ultra-low-power carbon nanotube FET-based quaternary logic gates 2016, https://doi.org/10.1080/21681724.2016.1138506
  8. Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET vol.27, pp.04, 2018, https://doi.org/10.1142/S0218126618500639
  9. Impact of Channel, Stress-Relaxed Buffer, and S/D Si1−xGex Stressor on the Performance of 7-nm FinFET CMOS Design with the Implementation of Stress Engineering 2018, https://doi.org/10.1007/s11664-017-6058-8
  10. Performance and Device Design Based on Geometry and Process Considerations for 14/16-nm Strained FinFETs vol.63, pp.3, 2016, https://doi.org/10.1109/TED.2016.2520583
  11. Interface states reduction in atomic layer deposited TiN/ZrO2/Al2O3/Ge gate stacks vol.36, pp.2, 2018, https://doi.org/10.1116/1.5006789
  12. Design and implementation of a low cost test bench to assess the reliability of FPGA vol.55, pp.9-10, 2015, https://doi.org/10.1016/j.microrel.2015.06.087
  13. New Methodology for the Design of Efficient Binary Addition Circuits in QCA vol.11, pp.6, 2012, https://doi.org/10.1109/TNANO.2012.2220565
  14. An efficient ternary serial adder based on carbon nanotube FETs vol.19, pp.1, 2016, https://doi.org/10.1016/j.jestch.2015.07.015
  15. Surface State Engineering of Metal/MoS2Contacts Using Sulfur Treatment for Reduced Contact Resistance and Variability vol.63, pp.6, 2016, https://doi.org/10.1109/TED.2016.2554149
  16. Analytical modeling of subthreshold characteristics by considering quantum confinement effects in ultrathin dual-metal quadruple gate (DMQG) MOSFETs vol.111, 2017, https://doi.org/10.1016/j.spmi.2017.07.032
  17. Nano-Scale Silicon Quantum Dot-Based Single-Electron Transistors and Their Application to Design of Analog-to-Digital Convertors at Room Temperature vol.26, pp.12, 2017, https://doi.org/10.1142/S0218126617502012
  18. Design and Evaluation of CNFET-Based Quaternary Circuits vol.31, pp.5, 2012, https://doi.org/10.1007/s00034-012-9413-2
  19. Some Device Design Considerations to Enhance the Performance of DG-MOSFETs vol.14, pp.6, 2013, https://doi.org/10.4313/TEEM.2013.14.6.291
  20. A Novel Design Approach for Ternary Compressor Cells Based on CNTFETs vol.35, pp.9, 2016, https://doi.org/10.1007/s00034-015-0197-z
  21. Landau levels, edge states, and magnetoconductance in GaAs/AlGaAs core-shell nanowires vol.87, pp.11, 2013, https://doi.org/10.1103/PhysRevB.87.115316
  22. A Degradation Model of Double Gate and Gate-All-Around MOSFETs With Interface Trapped Charges Including Effects of Channel Mobile Charge Carriers vol.14, pp.2, 2014, https://doi.org/10.1109/TDMR.2014.2310292
  23. Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length vol.38, pp.12, 2017, https://doi.org/10.1088/1674-4926/38/12/122002
  24. Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET vol.104, pp.2, 2017, https://doi.org/10.1080/00207217.2016.1199052
  25. 1/f noise in advanced CMOS transistors vol.14, pp.1, 2011, https://doi.org/10.1109/MIM.2011.5704805
  26. Efficient CNTFET-based Ternary Full Adder Cells for Nanoelectronics vol.3, pp.1, 2011, https://doi.org/10.1007/BF03353650
  27. An Efficient 5-Input Exclusive-OR Circuit Based on Carbon Nanotube FETs vol.36, pp.1, 2014, https://doi.org/10.4218/etrij.14.0113.0051
  28. Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits vol.53, 2016, https://doi.org/10.1016/j.mejo.2016.04.016
  29. A Threshold Voltage Model of Silicon-Nanotube-Based Ultrathin Double Gate-All-Around (DGAA) MOSFETs Incorporating Quantum Confinement Effects vol.16, pp.5, 2017, https://doi.org/10.1109/TNANO.2017.2717841
  30. Interfacial bonding and electronic structure of GaN/GaAs interface: A first-principles study vol.117, pp.13, 2015, https://doi.org/10.1063/1.4916724
  31. High Performance HfO2 Back Gated Multilayer MoS2 transistors 2016, https://doi.org/10.1109/LED.2016.2553059
  32. Radix-8 full adder in QCA with single clock-zone carry propagation delay vol.51, 2017, https://doi.org/10.1016/j.micpro.2017.04.005
  33. The Quasi-Neutral Limit in Optimal Semiconductor Design vol.55, pp.4, 2017, https://doi.org/10.1137/15M1051877
  34. Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone-Based Crossover vol.14, pp.3, 2015, https://doi.org/10.1109/TNANO.2015.2409117
  35. Device and circuit performance of Si-based accumulation-mode CGAA CMOS inverter vol.66, 2017, https://doi.org/10.1016/j.mssp.2017.04.005
  36. Coplanar wire crossing in quantum cellular automata using a ternary cell vol.7, pp.5, 2013, https://doi.org/10.1049/iet-cds.2012.0366
  37. Review of contact-resistance analysis in nano-material vol.32, pp.2, 2018, https://doi.org/10.1007/s12206-018-0101-9
  38. A new twelve-transistor approximate 4:2 compressor in CNTFET technology pp.1362-3060, 2018, https://doi.org/10.1080/00207217.2018.1545930
  39. Design of a Multi-digit Binary-to-Ternary Converter Based on CNTFETs pp.1531-5878, 2019, https://doi.org/10.1007/s00034-018-0977-3
  40. Performance Analysis in Digital Circuits for Process Corner Variations, Slew-Rate and Load Capacitance vol.103, pp.1, 2018, https://doi.org/10.1007/s11277-018-5428-8
  41. Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata pp.1793-6454, 2018, https://doi.org/10.1142/S021812661950141X
  42. Optimization of 7 nm Strained Germanium FinFET Design Parameters Using Taguchi Method and Pareto Analysis of Variance vol.7, pp.4, 2018, https://doi.org/10.1149/2.0081804jss
  43. DISC-FETs: Dual Independent Stacked Channel Field-Effect Transistors vol.39, pp.8, 2018, https://doi.org/10.1109/LED.2018.2851191
  44. Progress in Contact, Doping and Mobility Engineering of MoS2: An Atomically Thin 2D Semiconductor vol.8, pp.8, 2018, https://doi.org/10.3390/cryst8080316
  45. Ultrathin Vapor–Liquid–Solid Grown Titanium Dioxide-II Film on Bulk GaAs Substrates for Advanced Metal–Oxide–Semiconductor Device Applications vol.65, pp.4, 2018, https://doi.org/10.1109/TED.2018.2802490
  46. gate stack graded channel dual material trigate MOSFET vol.39, pp.12, 2018, https://doi.org/10.1088/1674-4926/39/12/124016
  47. A Novel Multiplexer-Based Quaternary Full Adder in Nanoelectronics pp.1531-5878, 2019, https://doi.org/10.1007/s00034-019-01039-8