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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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A novel approach for designing of variability aware low-power logic gates

  • Sharma, Vijay Kumar (School of Electronics & Communication Engineering, Shri Mata Vaishno Devi University)
  • Received : 2020.05.16
  • Accepted : 2021.08.03
  • Published : 2022.06.10
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Abstract

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

Keywords

Acknowledgement

The author thanks the editor and reviewers for their helpful comments and suggestions.

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