• 전자공학회논문지
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• 제50권9호
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• pp.55-59
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• 2013

Sub-$0.1{\mu}m$로 스케일이 감소함에 따라 기생 저항 효과가 크게 발생되는 dc Ids 측정 데이터 없이 측정 S-파라미터로부터 얻어진 RF Ids를 사용하여 벌크 MOSFET의 포화영역에서 게이트 전압 종속 유효 캐리어 속도를 추출하는 새로운 방법이 개발되었다. 이 방법은 바이어스 종속 기생 게이트-소스 캐패시턴스와 유효 채널 길이의 복잡한 추출 없이 포화영역의 유효 캐리어 속도를 추출할 수 있게 한다. 이러한 RF 기술을 사용하여 벌크 포화 속도를 초과하는 전자 속도 overshoot 현상이 $0.065{\mu}m$ 게이트 길이의 벌크 N-MOSFET에서 관찰되었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.36-36
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• 2009

In this work, we describe a method to fabricate the Pt-silicided SB-MOSFETs with a n-type Silicon-On-Insulator (SOI) substrate as an active layer and demonstrate their electrical and structural properties. The fabricated SB-MOSFETs have novel structure and metal gate without sidewall. The gate oxide with a thickness of 7 nm was deposited by sputtering. Also, this fabrication processes were carried out below $500^{\circ}C$. As a result, Subthreshold swing value and on/off ratio of Fabricated SB MOSFETs was 70 [mV/dec] and $10^8$.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2843-2846
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• 2003

This paper proposes a PWM(Pulse Width Modulation) circuit using CMOS OTA with a single-voltage supply. The OTA employed has an input stage which consists of a pair of two MOSFETs operating in plural operation regions. The MOSFETs work complemetarily and realize a rail-to-rail input range. The input stage requires no matching of an n-channel type input circuit and a p-channel type input circuit unlike conventional rail-to-rail input stages because the input stage is realized by single channel type MOSFETs. In order to confirm the validity of the proposed circuit, it is simulated by H-SPICE program. Futhermore, the proposed circuit will be integrated on chip using 0.35 $\mu\textrm{m}$ CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.221-226
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• 2008

A new two dimensional (2-D) analytical model for the Threshold Voltage on dual material surrounding gate (DMSG) MOSFETs is presented in this paper. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. The simple and accurate analytical expression for the threshold voltage and sub-threshold swing is derived. It is seen that short channel effects (SCEs) in this structure is suppressed because of the perceivable step in the surface potential which screens the drain potential. We demonstrate that the proposed model exhibits significantly reduced SCEs, thus make it a more reliable device configuration for high speed wireless communication than the conventional single material surrounding gate (SMSG) MOSFETs.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.649-654
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• 2014

In this paper, an analytical model for Surrounding Gate (SG) metal-oxide- semiconductor field effect transistors (MOSFETs) considering quantum effects is presented. To achieve this goal, we have used variational approach for solving the Poission and Schrodinger equations. This model is developed to provide an analytical expression for inversion charge distribution function for all regions of device operation. This expression is used to calculate the other important parameters like inversion charge density, threshold voltage, drain current and gate capacitance. The calculated expressions for the above parameters are simple and accurate. This paper also focuses on the gate tunneling issue associated with high dielectric constant. The validity of this model was checked for the devices with different dimensions and bias voltages. The calculated results are compared with the simulation results and they show good agreement.

• 전자공학회논문지A
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• 제33A권10호
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• pp.130-138
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• 1996

The size of a device needs to scale down to increase its integrity and speed. As the size of the device is reduced, the hot-carrier degradation that severely effects on device reliabilty is concerned. In this paper, sub-micron buried-channel P-MOSFETs were fabircated, and the hot-carrier effects were invetigated. Also the hot-carrier effect in the buired-channel P-MOSFETs and the surface-channel P-MOSFETs were compared with simulation programs using SUPREM-4 and MINIMOS-4. This paper showed that the electric characteristics of sub-micron P-MOSFET are different from those of N-MOSFET. Also it showed that the punchthrough voltage ( $V_{pt}$ ) was abruptly drop after applying the stress and became almost 0V when the channel lengths were shorter than 0.6.mu.m. The lower punchthrough voltage causes the device to operte poorly by the deterioration of cut-off characteries in the switching mode. We can conclude that the buried channel P-MOSFET for CMOS circuits has a limit of the channel length to be around 0.6.mu.m.

• 한국진공학회지
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• 제17권3호
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• pp.199-203
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• 2008

$O_2$ 플라즈마를 이용한 표면처리 공정이 Bio-FET (biologically sensitive field-effect transistor)에 미치는 영향을 조사하기 위하여, SOI (Silicon-on-Insulator) wafer와 sSOI (strained- Si-on-Insulator) wafer를 이용하여 pseudo-MOSFET을 제작하고 $O_2$ 플라즈마를 이용하여 표면처리를 진행하였다. 제작된 시료들은 back gated metal contact junction 방식으로 측정되었다. $I_D-V_G$ 특성과 field effect mobility 특성의 관찰을 통하여 $O_2$ 플라즈마 표면처리에 따른 각 시료들의 전기적 특성 변화에 대하여 관찰하였다. 그리고 $O_2$ 플라즈마 표면처리 과정에서 플라즈마에 의한 손상을 받은 시료들은 2% 수소희석가스 ($H_2/N_2$)를 이용한 후속 열처리 공정을 진행한 후 전기적 특성이 향상되는 것을 관찰할 수 있었다. 이는 수소희석가스를 이용한 후속 열처리 공정을 통하여 산화막과 Si 사이의 계면 준위와 산화막 내부의 전하 포획 준위를 감소시켰기 때문이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.283-287
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• 2017

Recently, Ni-InGaAs has been required for high-performance III-V MOSFETs as a promising self-aligned material for doped source/drain region. As downscaling of device proceeds, reduction of contact resistance ($R_c$) between Ni-InGaAs and n-InGaAs has become a challenge for higher performance of MOSFETs. In this paper, we compared three types of sample, vacuum, 2% $H_2$ and 4% $H_2$ annealing condition in rapid thermal annealing (RTA) step, to verify the reduction of $R_c$ at Ni-InGaAs/n-InGaAs interface. Current-voltage (I-V) characteristic of metal-semiconductor contact indicated the lowest $R_c$ in 4% $H_2$ sample, that is, higher current for 4% $H_2$ sample than other samples. The result of this work could be useful for performance improvement of InGaAs n-MOSFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.210-214
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• 2016

In this paper, the decrease in the contact resistance of Ni germanide/Ge contact was studied as a function of the thickness of the antimony (Sb) interlayer for high performance Ge MOSFETs. Sb layers with various thickness of 2, 5, 8 and 12 nm were deposited by RF-Magnetron sputter on n-type Ge on Si wafers, followed by in situ deposition of 15nm-thick Ni film. The contact resistance of samples with the Sb interlayer was lower than that of the reference sample without the Sb interlayer. We found that the Sb interlayer can lower the contact resistance of Ni germanide/Ge contact but the reduction of contact resistance becomes saturated as the Sb interlayer thickness increases. The proposed method is useful for high performance n-channel Ge MOSFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.518-524
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• 2014

The substrate doping concentration dependence of strain-enhanced electron mobility in (110)/<110> nMOSFETs is investigated by using a self-consistent Schr$\ddot{o}$dinger-Poisson solver. The electron mobility model includes Coulomb, phonon, and surface roughness scattering. The calculated results show that, in contrast to (100)/<110> case, the longitudinal tensile strain-induced electron mobility enhancement on the (110)/<110> can be increased at high substrate doping concentration.