• The Journal of the Korea institute of electronic communication sciences
• /
• v.9 no.7
• /
• pp.747-752
• /
• 2014

This paper relates 10% shrink from $0.13{\mu}m$ design for logic devices as well as input and output (I/O) circuits, different from the previous shrink methodologies which shrink only core device. Thin gate oxide was changed to decoupled plasma nitridation(DPN) oxide as a thin gate oxide (1.2V) to reduce the flicker noise, resulting in three to five times lower flicker noise than pre-shrink process. Unavoidable issue by shrink is capacitor for this normally metal insulator metal (MIM). To solve this issue, 20% higher unit MIM capacitor ($1.2fF/{\mu}m^2$) was developed and its performance were evaluated.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.3 no.2
• /
• pp.471-475
• /
• 1999

The metal plasma-etch damage immunity of nMOSFET with $N{_2}O$ gate oxide is found to be improved comparing to that with regular pure oxide of similar thickness. With increasing the antenna ratio (AR), the characteristics of nMOSFETs with $N{_2}O$ oxide shows tighter initial distribution and smaller degradation under constant field stress, which is explained by the effect of the nitrogen at the substrate $Si/SiO_2$ interface. Also, if $N{_2}O$ gate oxide is used, the maximum allowable size of metal AAR and PAR may be increased to the much larger values. These improvements of nMOSFETs with $N{_2}O$ gate oxide are attributed to the effect of the interface hardness improved by the nitrogen included at the substrate-Si/$N{_2}O$-oxide interface.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.1 no.1
• /
• pp.31-39
• /
• 2001

W polymetal gate technology for giga bit DRAM are presented. Key module processes for polymetal gate are studied in detail. $W/WN_x/poly-silicon$ adopted for a word line of 256Mbit DRAM has good gate oxide integrity and junction leakage characteristics through full integration, which is comparable to those of conventional $WSi_x$/Poly-silicon gate process. These results undoubtedly show that $W/WN_x/poly-silicon$ is the strongest candidate as a word line for Giga bit DRAM.

• Journal of the Microelectronics and Packaging Society
• /
• v.27 no.1
• /
• pp.31-35
• /
• 2020

This study demonstrates metal-oxide based memtransistor device and the gate tunable memristive characteristic using atomic layer deposition (ALD) and ZnO n-type oxide semiconductor. We fabricated a memtransistor device having channel width 70 ㎛, channel length 5 ㎛, back gate, using 40 nm thick ZnO thin film, and measured gate-tunable memristive characteristics at each gate voltage (50V, 30V, 10V, 0V, -10V, -30V, -50V) under humidity of 40%, 50%, 60%, and 70% respectively, in order to investigate the relation between a memristive characteristic and hydrogen doping effect on the ZnO memtransistor device. The electron mobility and gate controllability of memtransistor device decreased with an increase of humidity due to increased electron carrier concentration by hydrogen doping effect. The gate-tunable memristive characteristic was observed under humidity of 60% 70%. Resistive switching ratio increased with an increase of humidity while it loses gate controllability. Consequently, we could obtain both gate controllability and the large resistive switching ratio under humidity of 60%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1999.11a
• /
• pp.44-48
• /
• 1999

In order to the investigate for the DC(forward-reverse) breakdown properties of gate oxide in MOSFET, we are manufactured the specimen as following. The resistivity is 1.2($\Omega$ $.$ cm), 1.5($\Omega$ $.$ cm) and 1.8($\Omega$ $.$ cm) when thickness is 600(${\AA}$), and the diffusion time is both 110[min] and 150[min] when thickness is 600[${\AA}$]. In DC dielectric strength due to the each resistivity, it is confirmed that almost of the leakage current and breakdown current is flowed through n+ source when positive bias is applied, but is flowed through P region when negative bias is applied. It is thought that the dielectric strength due to the diffusion time is the contribution as increasing of p region.

• Journal of Sensor Science and Technology
• /
• v.28 no.1
• /
• pp.17-22
• /
• 2019

As CMOS technology scales down, reliability is becoming an important concern for VLSI designers. This paper analyzes gate-oxide breakdowns (i.e., the time-dependent dielectric-breakdown (TDDB) aging effect) as a reliability issue for combinational circuits with 45-nm technology. This paper shows simulation results for the noise margin, delay, and power using a single inverter-chain circuit, as well as the International Symposium on Circuits and Systems (ISCAS)'85 benchmark circuits. The delay and power variations in the presence of TDDB are also discussed in the paper. Finally, we propose a novel method to compensate for the logic failure due to dielectric breakdowns: We used a higher supply voltage and a negative ground voltage for the circuit. The proposed method was verified using the ISCAS'85 benchmark circuits.

• Korean Journal of Materials Research
• /
• v.13 no.11
• /
• pp.711-716
• /
• 2003

Gate length, height, and silicide thickness have all been shrinking linearly as device density has progressively increased over the years. We investigated the effect of the cobalt diffusion during the silicide formation process on the 60$\AA$-thick gate oxide lying underneath the Ti/Co and Co/Ti bilayers. We prepared four different cobalt silicides, which have similar sheet resistance, made from the film structure of Co/Ti(interlayer), and Ti(capping layer)/Co, and peformed the current-voltage, time-to-break down, and capacitance-voltage measurements. Our result revealed that the cobalt silicide process without the Ti capping layer allowed cobalt atoms to diffuse into the upper interface of gate oxides. We propose that 100$\AA$-thick titanium interlayer may lessen the diffusion of cobalt to gate oxides in 1500-$\AA$ height polysilicon gates.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.34D no.9
• /
• pp.56-63
• /
• 1997

There generally exists a large variation in the thereshold voltages of the flash EEPROM cells after they are erased by using th fowler-nordheim tunneling, thereby getting some cells to be overeased. If the overerased cells are programmed with the conventional one-step programming scheme where an 12-13V pulse with the duration of 100.mu.S is applie don the control gate for the programming, they can suffer from the significant degradation of the reliability of the gate oxide. A two-step programming schem, where an 8/12 V pulse with a duration of 50.mu.S for each voltage is applied on the control gate for the programming, has been studied to solve the problem. The experimental results hav eshown that there is little difference in the programming characteristics between those two schemes, whereas the degradation of the gate oxide due to the programming can be significantly reduced with the two-step programming scheme compared to that with the one-step programming scheme. This is possibly because the positive charge stored in the floating gate of the overerased cells is compensate dwith the electrons injected into the floating gate while the 8V pulse is applied on the control gate, which leaves the overerased cells in the normally erased state after the duration of the 8V pulse.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.10
• /
• pp.54-61
• /
• 2011

In this paper, a simple analytical model for deriving the I-V characteristics of a cylindrical surrounding gate SOI MOSFET with intrinsic silicon core is suggested. The Poisson equation in the intrinsic silicon core and the Laplace equation in the gate oxide layer are solved analytically. The surface potentials at both source and drain ends are obtained by means of the bisection method. From them, the surface potential distribution is used to describe the I-V characteristics in a closed-form. Simulation results seem to show the dependencies of the I-V characteristics on the various device parameters and applied bias voltages within a range of satisfactory accuracy.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.4
• /
• pp.278-286
• /
• 2011

In this paper, we present a compact model of gate-voltage-dependent quantum effects in short-channel surrounding-gate (SG) metal-oxide-semiconductor field-effect transistors (MOSFETs). We based the model on a two-dimensional (2-D) analytical solution of Poisson's equation using cylindrical coordinates. We used the model to investigate the electrostatic potential and current sensitivities of various gate lengths ($L_g$) and radii (R). Schr$\ddot{o}$dinger's equation was solved analytically for a one-dimensional (1-D) quantum well to include quantum effects in the model. The model takes into account quantum effects in the inversion region of the SG MOSFET using a triangular well. We show that the new model is in excellent agreement with the device simulation results in all regions of operation.