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A study on Flicker Noise Improvement by Decoupled Plasma Nitridation

Decoupled Plasma Nitridation에 의한 Flicker 노이즈 개선에 관한 연구

  • 문성열 (전남대학교 전기 및 반도체공학과) ;
  • 강성준 (전남대학교 전기 및 반도체공학과) ;
  • 정양희 (전남대학교 전기 및 반도체공학과)
  • Received : 2014.05.30
  • Accepted : 2014.07.11
  • Published : 2014.07.31

Abstract

This paper relates 10% shrink from $0.13{\mu}m$ design for logic devices as well as input and output (I/O) circuits, different from the previous shrink methodologies which shrink only core device. Thin gate oxide was changed to decoupled plasma nitridation(DPN) oxide as a thin gate oxide (1.2V) to reduce the flicker noise, resulting in three to five times lower flicker noise than pre-shrink process. Unavoidable issue by shrink is capacitor for this normally metal insulator metal (MIM). To solve this issue, 20% higher unit MIM capacitor ($1.2fF/{\mu}m^2$) was developed and its performance were evaluated.

본 논문은 $0.13{\mu}m$ 기술의 디자인을 10% 축소하는데 기존의 로직 디바이스만의 축소와는 달리 로직뿐 아니라 입, 출력 회로의 축소에 관한 것이다. 게이트 산화막(1.2V)을 decoupled plasma nitridation(DPN) oxide로 변경함으로써 flicker 노이즈를 축소 전 공정에 비해 1/3-1/5배 감소됨을 확인하였다. 또한, 축소에 의한 피할 수 없는 문제는 일반적인 metal insulator metal(MIM)의 캐패시터 문제이다. 이를 해결하기 위하여 20% 높은 MIM 캐패시터($1.2fF/{\mu}m^2$)를 개선하고 그 특성을 평가하였다.

Keywords

References

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