Browse > Article
http://dx.doi.org/10.13067/JKIECS.2014.9.7.747

A study on Flicker Noise Improvement by Decoupled Plasma Nitridation  

Mun, Seong-Yeol (전남대학교 전기 및 반도체공학과)
Kang, Seong-Jun (전남대학교 전기 및 반도체공학과)
Joung, Yang-Hee (전남대학교 전기 및 반도체공학과)
Publication Information
The Journal of the Korea institute of electronic communication sciences / v.9, no.7, 2014 , pp. 747-752 More about this Journal
Abstract
This paper relates 10% shrink from $0.13{\mu}m$ design for logic devices as well as input and output (I/O) circuits, different from the previous shrink methodologies which shrink only core device. Thin gate oxide was changed to decoupled plasma nitridation(DPN) oxide as a thin gate oxide (1.2V) to reduce the flicker noise, resulting in three to five times lower flicker noise than pre-shrink process. Unavoidable issue by shrink is capacitor for this normally metal insulator metal (MIM). To solve this issue, 20% higher unit MIM capacitor ($1.2fF/{\mu}m^2$) was developed and its performance were evaluated.
Keywords
Flicker Noise; Gate Oxide; Shrink;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
1 I. Bloom and Y. Nemirovsky, "1=f noise reduction of metal-oxide-semiconductor transistors by cycling from inversion to accumulation," Appl. Phys. Lett., vol. 58, no. 15, 1991, pp. 1664-1666.   DOI
2 Y. Tsividis, "Analysis and Design of Analog Integrated Circuits," Solid-State Circuits Mag. IEEE, vol. 6, no. 1, 2014, pp. 37-38.   DOI
3 C. Hu, G. P. Li, E. Worley, and J. White, "Consideration of low-frequency noise in MOSFET'' s for analog performance," IEEE Electron Device Lett., vol. 17, no. 12, 1996, pp. 552-554.   DOI
4 K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, "A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors," IEEE Trans. Electron Devices, vol. 37, no. 3, 1990, pp. 654-665.   DOI   ScienceOn
5 B. Dierickx and E. Simoen, "The decrease of ''random telegraph signal,'' noise in metal- oxide-semiconductor field-effect transistors when cycled from inversion to accumulation," J. Appl. Phys., vol. 71, no. 4, 1992, pp. 2028-2029.   DOI
6 H. J. Chung, "5-TFT OLED Pixel Circuit Compensating Threshold Voltage Variation of p-channel Poly-Si TFTs," J. of The Korea Institute of Electronic Communication Sciences, vol. 9, no. 3, 2014, pp. 279-284.   과학기술학회마을   DOI
7 H. J. Chung, "A Voltage Programming AMOLED Pixel Circuit Compensating Threshold Voltage Variation of n-channel Poly-Si TFTs," J. of The Korea Institute of Electronic Communication Sciences, vol. 8, no. 2, 2013, pp. 207-212.   과학기술학회마을   DOI   ScienceOn
8 B. Razavi, "A study of phase noise in CMOS oscillators," IEEE J. Solid state Circuit, vol. 31, 1996, pp. 331-343.   DOI   ScienceOn
9 T. Boutchacha, G. Ghibaudo, G. Guegan, and T. Skotnicki, "Low frequency noise characterization of 0.18 um Si CMOS transistors," Microelectron. Reliab., vol. 37, no. 10/11, 1997, pp. 1599-1602.   DOI
10 T. Strom and S. Signell, "Analysis of periodically switched linear circuits," IEEE Trans. Circuits Syst., vol. 24, 1977, pp. 531-541.   DOI
11 H. Tian, B. Fowler, and A. El Gamal, "Analysis of temporal noise in CMOS APS," In Proc. SPIE, vol. 3649, San Jose, CA, Jan. 1999, pp. 177-185.
12 C. Jakobson, I. Bloom, and Y. Nemirovsky, "1=f noise in CMOS transistors for analog applications from subthreshold to saturation," J. of Solid-State Electron., vol. 42, no. 10, 1998, pp. 1807-1817.   DOI