[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.5369/JSST.2019.28.1.17

Analysis of Gate-Oxide Breakdown in CMOS Combinational Logics

Kim, Kyung Ki (Department of Electronic Engineering, Daegu Unversity)

Publication Information

Journal of Sensor Science and Technology / v.28, no.1, 2019 , pp. 17-22 More about this Journal

Abstract

As CMOS technology scales down, reliability is becoming an important concern for VLSI designers. This paper analyzes gate-oxide breakdowns (i.e., the time-dependent dielectric-breakdown (TDDB) aging effect) as a reliability issue for combinational circuits with 45-nm technology. This paper shows simulation results for the noise margin, delay, and power using a single inverter-chain circuit, as well as the International Symposium on Circuits and Systems (ISCAS)'85 benchmark circuits. The delay and power variations in the presence of TDDB are also discussed in the paper. Finally, we propose a novel method to compensate for the logic failure due to dielectric breakdowns: We used a higher supply voltage and a negative ground voltage for the circuit. The proposed method was verified using the ISCAS'85 benchmark circuits.

Keywords

TDDB; gate-oxide breakdown; aging effect;

Citations & Related Records

Reference

1	T. Nigam, A. Kerber, P. Peumans, "Accurate model for time-dependent dielectric breakdown of high-k metal gate stacks," in Proc. Intl. Reliability Physics Symposium, pp. 523-530, 2009.
2	B. Kaczer, R. Degraeve, "Gate oxide breakdown in FET devices and circuits: From nanoscale physics to systemlevel reliability," in Microelectronics Reliability, vol. 47, pp. 559-566, May 2007. DOI
3	J. Fang, S.S. Sapatnekar, "Scalable methods for the analysis and optimization of gate oxide breakdown," in Quality Electronic Design (ISQED), pp. 638-645, 2010.
4	H. Wang, M. Miranda, F. Catthoor, D. Wim, "Impact of random soft oxide breakdown on SRAM energy/delay drift," IEEE Trans. Device and Mater. Rel., Vol. 7, No. 4, pp. 581-591, December 2007. DOI
5	T. Wee Chen, Y. M. Kim, K. Kim, Y. Kameda, M. Mizuno, S. Mitra, "Experimental study of gate-oxide early life failures," in Proc. Intl. Reliability Physics Symposium, pp. 650-658, 2009.
6	S.S. Lombardo, J.H. Stathis, B.P. Linder, K.L. Pey, F. Palumbo, C.H. Tung, "Dielectric breakdown mechanisms in gate oxides," Journal of Applied Physics, Vol. 98, No. 12, pp. 1-36, 2005. DOI
7	B. Kacze, R. Degraeve, M. Rasras, K. V. de Mieroop, P. J. Roussel, G. Groeseneken, "Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability," IEEE Trans. Electron Devices, Vol. 49, pp. 500-506, 2002. DOI
8	R. Rodriguez, R.V. Joshi, J.H. Stathis, C.T. Chuang, "Oxide breakdown model and its impact on SRAM cell functionality," in Simulation of Semiconductor Processes and Devices, pp. 283-286, 2003.
9	M. Choudhury, V. Chandra, K. Mohanram, R. Aitken, "Analytical model for TDDB-based performance degradation in combinational logic," in Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 423-428, 2010.
10	J.H. Stathis, "Physical and predictive models of ultra thin oxide reliability in CMOS devices and circuits," in Proc. Intl. Reliability Physics Symposium, pp. 132-149, 2001.