Journal of Sensor Science and Technology (센서학회지)

The Korean Sensors Society (한국센서학회)
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Analysis of Gate-Oxide Breakdown in CMOS Combinational Logics

  • Kim, Kyung Ki (Department of Electronic Engineering, Daegu Unversity)
  • Received : 2019.01.24
  • Accepted : 2019.01.30
  • Published : 2019.01.31
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Abstract

As CMOS technology scales down, reliability is becoming an important concern for VLSI designers. This paper analyzes gate-oxide breakdowns (i.e., the time-dependent dielectric-breakdown (TDDB) aging effect) as a reliability issue for combinational circuits with 45-nm technology. This paper shows simulation results for the noise margin, delay, and power using a single inverter-chain circuit, as well as the International Symposium on Circuits and Systems (ISCAS)'85 benchmark circuits. The delay and power variations in the presence of TDDB are also discussed in the paper. Finally, we propose a novel method to compensate for the logic failure due to dielectric breakdowns: We used a higher supply voltage and a negative ground voltage for the circuit. The proposed method was verified using the ISCAS'85 benchmark circuits.

Keywords

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Fig. 1. TDDB effect, cross-section view

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Fig. 2. TDDB model for NMOS

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Fig. 3. Single-path model

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Fig. 4. Dual-path model

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Fig. 5. Noise-margin analysis

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Fig. 6. Power vs. reverse-body biasing

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Fig. 7. Delay vs. reverse body biasing

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Fig. 8. Input and output waveform before HBD

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Fig. 9. Input and output waveform after HBD

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Fig. 10. Input and output waveform before HBD

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Fig. 11. Input and output waveform after HBD

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Fig. 12. Input and output waveform after compensation

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Fig. 13. c3540 circuit Output waveform after compensation

Table 1. Simulation Results for Inverter Chain with TDDB

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