• Title/Summary/Keyword: dual fuse

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Experimental investigations on resilient beam-column end-plate connection with structural fuse

  • Arunkumar Chandrasekaran;Umamaheswari Nambiappan
    • Steel and Composite Structures
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    • v.47 no.3
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    • pp.315-337
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    • 2023
  • The steel structure is an assembly of individual structural members joined together by connections. The connections are the focal point to transfer the forces which is susceptible to damage easily. It is challenging to replace the affected connection parts after an earthquake. Hence, steel plates are utilised as a structural fuse that absorbs connection forces and fails first. The objective of the present research is to develop a beam-column end plate connection with single and dual fuse and study the effect of single fuse, dual fuse and combined action of fuse and damper. In this research, seismic resilient beam-column end plate connection is developed in the form of structural fuse. The novel connection consists of one main fuse was placed horizontally and secondary fuse was placed vertically over main fuse. The specimens are fabricated with the variation in number of fuse (single and dual) and position of fuse (beam flange top and bottom). From the fabricated ten specimens five specimens were loaded monotonically and five cyclically. The experimental results are compared with Finite Element Analysis results of Arunkumar and Umamaheswari (2022). The results are critically assessed in the aspect of moment-rotation behaviour, strain in connection components, connection stiffness, energy dissipation characteristics and ductility. While comparing the performance of total five specimens, the connection with fuse exhibited superior performance than the conventional connection. An equation is proposed for the moment of resistance of end-plate connection without and with structural fuse.

Deign of Small-Area Dual-Port eFuse OTP Memory IP for Power ICs (PMIC용 저면적 Dual Port eFuse OTP 메모리 IP 설계)

  • Park, Heon;Lee, Seung-Hoon;Park, Mu-Hun;Ha, Pan-Bong;Kim, Young-Hee
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.8 no.4
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    • pp.310-318
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    • 2015
  • In this paper, dual-port eFuse OTP (one-time programmable) memory cells with smaller cell sizes are used, a single VREF (reference voltage) is used in the designed eFuse OTP IP (intellectual property), and a BL (bit-line) sensing circuit using a S/A (sense amplifier) based D F/F is proposed. With this proposed sensing technique, the read current can be reduced to 3.887mA from 6.399mA. In addition, the sensing resistances of a programmed eFuse cell in the program-verify-read and read mode are also reduced to $9k{\Omega}$ and $5k{\Omega}$ due to the analog sensing. The layout size of the designed 32-bit eFuse OTP memory is $187.845{\mu}m{\times}113.180{\mu}m$ ($=0.0213{\mu}m2$), which is confirmed to be a small-area implementation.

Design of a 32-Bit eFuse OTP Memory for PMICs (PMIC용 32bit eFuse OTP 설계)

  • Kim, Min-Sung;Yoon, Keon-Soo;Jang, Ji-Hye;Jin, Liyan;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.10
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    • pp.2209-2216
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    • 2011
  • In this paper, we design a 32-bit eFuse OTP memory for PMICs using MagnaChip's $0.18{\mu}m$ process. We solve a problem of an electrical shortage between an eFuse link and the VSS of a p-substrate in programming by placing an n-well under the eFuse link. Also, we propose a WL driver circuit which activates the RWL (read word-line) or WWL (write word-line) of a dual-port eFuse OTP memory cell selectively when a decoded WERP (WL enable for read or program) signal is inputted to the eFuse OTP memory directly. Furthermore, we reduce the layout area of the control circuit by removing a delay chain in the BL precharging circuit. We'can obtain an yield of 100% at a program voltage of 5.5V on 94 manufactured sample dies when measured with memory tester equipment.

Design of a redundancy control circuit for 1T-SRAM repair using electrical fuse programming (전기적 퓨즈 프로그래밍을 이용한 1T-SRAM 리페어용 리던던시 제어 회로 설계)

  • Lee, Jae-Hyung;Jeon, Hwang-Gon;Kim, Kwang-Il;Kim, Ki-Jong;Yu, Yi-Ning;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.8
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    • pp.1877-1886
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    • 2010
  • In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.

Design of High-Reliability eFuse OTP Memory for PMICs (PMIC용 고신뢰성 eFuse OTP 메모리 설계)

  • Yang, Huiling;Choi, In-Wha;Jang, Ji-Hye;Jin, Liyan;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.7
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    • pp.1455-1462
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    • 2012
  • In this paper, a BCD process based high-reliability 24-bit dual-port eFuse OTP Memory for PMICs is designed. We propose a comparison circuit at program-verify-read mode to test that the program datum is correct by using a dynamic pseudo NMOS logic circuit. The comparison result of the program datum with its read datum is outputted to PFb (pass fail bar) pin. Thus, the normal operation of the designed OTP memory can be verified easily by checking the PFb pin. Also we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse at program-verify-read mode. We design a 24-bit eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $289.9{\mu}m{\times}163.65{\mu}m$ ($=0.0475mm^2$).

PUF Logic Employing Dual Anti-fuse OTP Memory for High Reliability (신뢰성 향상을 위한 듀얼 안티퓨즈 OTP 메모리 채택 D-PUF 회로)

  • Kim, Seung Youl;Lee, Je Hoon
    • Convergence Security Journal
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    • v.15 no.3_1
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    • pp.99-105
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    • 2015
  • A typical SRAM-based PUF is used in random number generation and key exchange process. The generated out puts should be preserved, but the values are changed owing to the external environment. This paper presents a new D-PUF logic employing a dual anti-fuse OTP memory to the SRAM-based PUF. The proposed PUF can enhance the reliability of the logic since it can preserve the output values. First, we construct the OTP memory using an anti-fuse. After power up, a SRAM generates the random values owing to the mismatch of cross coupled inverter pair. The generated random values are programed in the proposed anti-fuse ROM. The values that were programed in the ROM at once will not be changed and returned. Thus, the outputs of the proposed D-PUF are not affected by the environment variable such as the operation voltage and temperature variation, etc. Consequently, the reliability of the proposed PUF will be enhanced owing to the proposed dual anti-fuse ROM. Therefore, the proposed D-PUF can be stably operated, in particular, without the powerful ECC in the external environment that are changed.

Design of low-power OTP memory IP and its measurement (저전력 OTP Memory IP 설계 및 측정)

  • Kim, Jung-Ho;Jang, Ji-Hye;Jin, Liyan;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.11
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    • pp.2541-2547
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    • 2010
  • In this paper, we propose a design technique which replaces logic transistors of 1.2V with medium-voltage transistors of 3.3V having small off-leakage current in repetitive block circuits where speed is not an issue, to implement a low-power eFuse OTP memory IP in the stand-by state. In addition, we use dual-port eFuse cells reducing operational current dissipation by reducing capacitances parasitic to RWL (Read word-line) and BL (Bit-line) in the read mode. Furthermore, we propose an equivalent circuit for simulating program power injected to an eFuse from a program voltage. The layout size of the designed 512-bit eFuse OTP memory IP with a 90nm CMOS image sensor process is $342{\mu}m{\times}236{\mu}m$. It is confirmed by measurement experiments on 42 samples with a program voltage of 5V that we get a good result having 97.6 percent of program yield. Also, the minimal operational supply voltage is measured well to be 0.9V.

Design of High-Reliability Differential Paired eFuse OTP Memory for Power ICs (Power IC용 고신뢰성 Differential Paired eFuse OTP 메모리 설계)

  • Park, Young-Bae;Jin, Li-Yan;Choi, In-Hwa;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.2
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    • pp.405-413
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    • 2013
  • In this paper, a high-reliability differential paired 24-bit eFuse OTP memory with program-verify-read mode for PMICs is designed. In the proposed program-verify-read mode, the eFuse OTP memory can do a sensing margin test with a variable pull-up load in consideration of programmed eFuse resistance variation and can output a comparison result through a PFb (pass fail bar) pin by comparing a programmed datum with its read one. It is verified by simulation results that the sensing resistance is lower with $4k{\Omega}$ in case of the designed differential paired eFuse OTP memory than $50k{\Omega}$ in case of its dual-port eFuse OTP memory.

Dual Exposure Fusion with Entropy-based Residual Filtering

  • Heo, Yong Seok;Lee, Soochahn;Jung, Ho Yub
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.11 no.5
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    • pp.2555-2575
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    • 2017
  • This paper presents a dual exposure fusion method for image enhancement. Images taken with a short exposure time usually contain a sharp structure, but they are dark and are prone to be contaminated by noise. In contrast, long-exposure images are bright and noise-free, but usually suffer from blurring artifacts. Thus, we fuse the dual exposures to generate an enhanced image that is well-exposed, noise-free, and blur-free. To this end, we present a new scale-space patch-match method to find correspondences between the short and long exposures so that proper color components can be combined within a proposed dual non-local (DNL) means framework. We also present a residual filtering method that eliminates the structure component in the estimated noise image in order to obtain a sharper and further enhanced image. To this end, the entropy is utilized to determine the proper size of the filtering window. Experimental results show that our method generates ghost-free, noise-free, and blur-free enhanced images from the short and long exposure pairs for various dynamic scenes.

Dual-Stream Fusion and Graph Convolutional Network for Skeleton-Based Action Recognition

  • Hu, Zeyuan;Feng, Yiran;Lee, Eung-Joo
    • Journal of Korea Multimedia Society
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    • v.24 no.3
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    • pp.423-430
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    • 2021
  • Aiming Graph convolutional networks (GCNs) have achieved outstanding performances on skeleton-based action recognition. However, several problems remain in existing GCN-based methods, and the problem of low recognition rate caused by single input data information has not been effectively solved. In this article, we propose a Dual-stream fusion method that combines video data and skeleton data. The two networks respectively identify skeleton data and video data and fuse the probabilities of the two outputs to achieve the effect of information fusion. Experiments on two large dataset, Kinetics and NTU-RGBC+D Human Action Dataset, illustrate that our proposed method achieves state-of-the-art. Compared with the traditional method, the recognition accuracy is improved better.