• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.85-90
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• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.

• ETRI Journal
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• v.42 no.5
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• pp.773-780
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• 2020

A 40 nm complementary metal oxide semiconductor carrier-aggregated drive amplifier with high linearity is presented for sub-GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1 dB compression point (P1dB) to support high-linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7 dBm with over 22.8 dBm of output 3rd-order intercept point up to 0.9 GHz and demonstrated a 55 dBc adjacent channel leakage ratio (ACLR) for the 802.11af with -5 dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier-aggregated drive amplifier that achieves the highest ACLR performance.

• ETRI Journal
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• v.26 no.1
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• pp.7-13
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• 2004

To improve the characteristics of breakdown voltage and specific on-resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon-on-insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on-resistance. The breakdown voltage and the specific on-resistance of the fabricated device is 352 V and $18.8 m{\Omega}{\cdot}cm^2$ with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on-state is over 200 V and the saturation current at $V_{gs}=5V$ and $V_{ds}$=20V is 16 mA with a gate width of $150{\mu}m$.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.167-170
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• 2002

The design and fabrication of Q-band 3-stage monolithic microwave integrated circuit(MMIC) driver and power amplifiers for WLAN are presented using 0.2${\mu}{\textrm}{m}$ AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor(PHEMT). In each stage of the MMIC DA, a negative feedback is used for both broadband and good stability. The MMIC PA has employed a balanced configuration to overcome these difficulties and achieve high power with low VSWR over a wide frequency range. In the MMIC DA, the measurement results arc achieved as an input return loss under -4dB, an output return loss under -l0dB, a gain of 14dB, and a PldB of 17dB at C-band(36~ 44GHz). The chip size is 28mm$\times$1.3mm. The developed MMIC PA has the l0dB linear gain over 360Hz to 420Hz band and 22dBm PldB performance at 400Hz. The size of fabricated MMIC PA is 4mm x3mm. These results closely match with design results. This MMIC DA Sl PA will be used as the unit cells to develop millimeter-wave transmitters for use in wideband wireless LAN systems.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.6
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• pp.1177-1182
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• 2018

We designed a 500W zero voltage switching DC / DC converter operating at 100Mhz with phase shift topology using UCC3895 driver. The dead time of the UCC3895 driver is designed so that the leading and lagging leg of the full bridge can be driven separately. So, the dead time can be given between the two legs separately. The dead time, which is an asymmetrical relationship between the two legs, enables the implementation of zero voltage switching. This paper proposed a negative feedback circuit design method for stable output voltage. The maximum efficiency of the prototype was 95.5% at $500{\Omega}$ load.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.11-13
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• 2019

This paper proposes a novel high step-up non-isolated DC-DC converter, suitable for regulating dc bus in various inherent low voltage micro sources especially for photovoltaic (PV) and fuel cell sources. This novel high voltage Non-isolated Boost DC-DC converter topology is best replacement, where high voltage conversion ratio is required without the transformer and also need continuous input current. Since the proposed topology utilizes the stack-based structure, the voltage gain, and the efficiency are higher than other conventional non-isolated converters. Switches in this topology is easier to control since its control signal is grounding reference. Also, there is no need of extra gate driver and extra power supply for driver circuit, which reduces the cost and size of system. In order to show the feasibility and practicality of the proposed topology principle operation, steady state analysis and simulation result is presented and analyzed in detail. To verify the performance of proposed converter and theoretical analysis 360W laboratory prototype is implemented.

• Journal of Information Display
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• v.13 no.2
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• pp.73-82
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• 2012

In this paper, a light-emitting diode (LED) backlight driver integrated circuit (IC) for medium-sized liquid crystal displays (LCDs) is proposed. In the proposed IC, a linear current regulator with matched internal resistors and an adaptive phase-shifted pulse-width modulation (PWM) dimming controller are also proposed to improve LED current uniformity and reliability. The double feedback loop control boost converter is used to achieve high power efficiency, fast transient characteristic, and high dimming frequency and resolution. The proposed IC was fabricated using the 0.35 ${\mu}m$ bipolar-CMOS-DMOS (BCD) process. The LED current uniformity and LED fault immunity of the proposed IC were verified through experiments. The measured power efficiency was 90%; the measured LED current uniformity, 97%; and the measured rising and falling times of the LED current, 86 and 7 ns, respectively. Due to the fast rising and falling characteristics, the proposed IC operates up to 39 kHz PWM dimming frequency, with an 8-bit dimming resolution. It was verified that the phase difference between the PWM dimming signals is changed adaptively when LED fault occurs. The experiment results showed that the proposed IC meets the requirements for the LED backlight driver IC for medium-sized LCDs.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.135-141
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• 2013

In this paper, we installed three high brightness red, green, and blue LED in one socket and made one pixel unit. And we also developed the full-color display board module and control unit which can express various images such as text, graphics, video image with the combination of pixel units and a number of modules. LED display driver module have a driver circuit within the combination of the RGB pixel dot on unit area. These modules of the existing form can be high priced because of implementation a fixed resolution in specific space and installation space. To overcome these shortcomings, we developed a LED driver and LED pixel modules free in array at random pitch intervals. Display board module of this paper enabled to display smoothly video image which have many data processing quantity through dragging data speed up 36 frames per second. Also there are an effect which is provided more clear image because of improving the flickering of the existing display board.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.31-39
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• 2009

This paper presents the single supply power line communication(PLC) SoC ASIC with built-in analog frond-end circuit. To achieve the low power consumption along with low chip cost, this PLC SoC ASIC employs fully CMOS analog front-end(AFE) and several built-in Regulators(LDOs) powering for Core logic, ADC, DAC and IP Pad driver. The AFE includes RX of pre-amplifier, Programmable gain amplifier and 10 bit ADC and TX of 10bit Digital Analog Converter and Line driver. This PLC Soc was implemented with 0.18um 1 Poly 5 Metal CMOS process. The single power supply of 3.3V is required for the internal LDOs. The total power consumption is below 30mA at standby and 300mA at active which meets the eco-design requirement. The chips size is $3.686\;{\times}\;2.633\;mm^2$.