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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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A dual-path high linear amplifier for carrier aggregation

  • Kang, Dong-Woo (AI Compact SoC Research Section, Electronics and Telecommunications Research Institute) ;
  • Choi, Jang-Hong (AI Compact SoC Research Section, Electronics and Telecommunications Research Institute)
  • Received : 2020.03.27
  • Accepted : 2020.07.02
  • Published : 2020.11.16
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Abstract

A 40 nm complementary metal oxide semiconductor carrier-aggregated drive amplifier with high linearity is presented for sub-GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1 dB compression point (P1dB) to support high-linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7 dBm with over 22.8 dBm of output 3rd-order intercept point up to 0.9 GHz and demonstrated a 55 dBc adjacent channel leakage ratio (ACLR) for the 802.11af with -5 dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier-aggregated drive amplifier that achieves the highest ACLR performance.

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References

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