A New SOI LDMOSFET Structure with a Trench in the Drift Region for a PDP Scan Driver IC

  • Son, Won-So (School of Electrical Engineering and Computer Science, Kyungpook National University) ;
  • Kim, Sang-Gi (Basic Research Laborotory, ETRI) ;
  • Sohn, Young-Ho (School of Electrical Engineering and Computer Science, Yeungnam University) ;
  • Choi, Sie-Young (School of Electrical Engineering and Computer Science, Kyungpook National University)
  • Received : 2003.09.09
  • Published : 2004.02.29

Abstract

To improve the characteristics of breakdown voltage and specific on-resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon-on-insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on-resistance. The breakdown voltage and the specific on-resistance of the fabricated device is 352 V and $18.8 m{\Omega}{\cdot}cm^2$ with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on-state is over 200 V and the saturation current at $V_{gs}=5V$ and $V_{ds}$=20V is 16 mA with a gate width of $150{\mu}m$.

Keywords

References

  1. Proc. ISPSD ‘98 High Voltage SOI CMOS IC Technology for Driving Plasma Display Panels Kenya Kobayashi;Hiroshi Yanagigawa;Kazuhisa Mori;Suichi Yamanaka;Akira Fujiwara
  2. Proc. ISPSD ‘93 Dependence of Breakdown Voltage on Drift Length and Buried Oxide Thickness in SOI RESURF LDMOS Transistor Merchant, S.;Arnold, E.;Baumgart, H.;Egloff, R.;Letavic, T.;Mukherjee, S.;Pein, H.
  3. IEEE IEDM Digest Integration of Power LDMOS into a Low-Voltage 0.5 mm BiCMOS Technology Tsui, P.G.Y.;Gilbert, P.V.;Sun, S.W.
  4. Proc. ISPSD ’97 A Novel High-Frequency LDMOS Transistor Using an Extended Gate RESURF Technology Vestling, L.;Edhholm, B.;Olsson, J.;Tiensuu, S.;Soderbrag, A.
  5. ETRI J. v.21 no.3 Characteristics of P-Channel SOI LDMOS Transistor with Tapered Field Oxides Kim, Jong-Dae;Kim, Sang-Gi;Roh, Tae-Moon;Park, Hoon-Soo;Koo, Jin- Gun;Kim, Dae-Yong
  6. ETRI J. v.25 no.3 Trenched-Sinker LDMOSFET (TS-LDMOS) Structure for 2 GHz Power Amplifiers Kim, Cheon-Soo;Kim, Sung-Do;Park, Mun-Yang;Yu, Hyun-Kyu
  7. ETRI J. v.24 no.4 Breakdown Voltage Improvement of p-LDMOSFET with an Uneven Racetrack Source for PDP Driver IC Applications Roh, Tae-Moon;Lee, Dae-Woo;Yang, Yil-Suk;Koo, Jin-Gun;Kim, Jong-Dae
  8. Proc. 1998 IEEE Int’l SOI Conf. 600 V Single-Chip Power Conversion System Based on Thin Layer Silicon-on-Insulator Letavic, T.;Arnold, E.;Simpson, M.;Peters, E.;Aquino, R.;Egloff, R.;Wong, S.;Mukherjee, S.
  9. IEDM Tech. Dig. Prospects of High Voltage Power ICs on Thin SOI (invited paper) Nakagawa, A.;Yasuhara, N.;Omura, I.;Yamaguchie,Y.;Ogura, T.;Matsudai, T.
  10. Proc. ISPSD ‘95 A Dielectric Isolated High-Voltage IC-Technology for Off-Line Applications Stoisiek, M.;Oppermaun, K.G.;Schwalke, U.;Takacs, D.
  11. Power Semiconductor Devices Baliga, B.J.
  12. ATHENA User’s Manual
  13. ETRI J. v.24 no.5 A Novel Process for Fabricating High Density Trench MOSFETs for DC-DC Converters Kim, Jong-Dae;Roh, Tae-Moon;Kim, Sang-Gi;Park, Il-Yong;Yang, Yil-Suk;Lee, Dae-Woo;Koo, Jin-Gun;Cho, Kyoung-Ik;Kang, Young-Il
  14. Microelectronics J. v.32 Silicon-on-Insulator Power Integrated Circuits Garner, D.M.;Udrea, F.;Lim, H.T.;Ensell, G.;Popescu, A.E.;Sheng, K.;Milne, W.I.
  15. Proc. ISPSD ’96 High Voltage LDMOS Transistors in Sub-Micron SOI Films Paul, A.K.;Leung, Y.K.;Plummer, J.D.;Wong, S.S.;Kuehne, S.C.;Huang, V.S.K.;Nguyen, C.T.